[PATCH RFC v2 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1

[Stephen Long]

Signed-off-by: Stephen Long <address@hidden>
---
 target/arm/helper-sve.h    |  3 +++
 target/arm/sve.decode      |  4 ++++
 target/arm/sve_helper.c    | 20 ++++++++++++++++++++
 target/arm/translate-sve.c | 30 ++++++++++++++++++++++++++++++
 4 files changed, 57 insertions(+)

diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 6cd6fdfae1..e509137e4a 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2697,3 +2697,6 @@ DEF_HELPER_FLAGS_3(sve2_aesimc, TCG_CALL_NO_RWG, void, 
ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(sve2_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(sve2_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(sve2_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 1cb5792bb1..278530ca83 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1435,3 +1435,7 @@ AESIMC          01000101 00 10000011100 1 00000 .....   
@rdn_e0
 AESE            01000101 00 10001 0 11100 0 ..... .....  @pd5_pn5_e0
 AESD            01000101 00 10001 0 11100 1 ..... .....  @pd5_pn5_e0
 SM4E            01000101 00 10001 1 11100 0 ..... .....  @pd5_pn5_e0
+
+## SVE2 crypto constructive binary operations
+SM4EKEY         01000101 00 1 ..... 11110 0 ..... .....  @rd_rn_rm_e0
+RAX1            01000101 00 1 ..... 11110 1 ..... .....  @rd_rn_rm_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 4204659276..8307abc401 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7542,3 +7542,23 @@ void HELPER(sve2_sm4e)(void *vd, void *vn, uint32_t desc)
         HELPER(crypto_sm4e)(vd + i, vn + i);
     }
 }
+
+void HELPER(sve2_sm4ekey)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc);
+    for (i = 0; i < opr_sz; i += 16) {
+        HELPER(crypto_sm4ekey)(vd + i, vn + i, vm + i);
+    }
+}
+
+void HELPER(sve2_rax1)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+    uint64_t *d = vd, *n = vn, *m = vm;
+
+    for (i = 0; i < opr_sz; ++i) {
+        uint64_t nn = n[i];
+        uint64_t mm = m[i];
+        d[i] = nn ^ rol64(mm, 1);
+    }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 6b26d8c512..2baa51b2b2 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7990,3 +7990,33 @@ static bool trans_SM4E(DisasContext *s, arg_rr_esz *a)
     }
     return true;
 }
+
+static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a)
+{
+    if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+        return false;
+    }
+    if (sve_access_check(s)) {
+        unsigned vsz = vec_full_reg_size(s);
+        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+                           vec_full_reg_offset(s, a->rn),
+                           vec_full_reg_offset(s, a->rm),
+                           vsz, vsz, 0, gen_helper_sve2_sm4ekey);
+    }
+    return true;
+}
+
+static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
+{
+    if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+        return false;
+    }
+    if (sve_access_check(s)) {
+        unsigned vsz = vec_full_reg_size(s);
+        tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+                           vec_full_reg_offset(s, a->rn),
+                           vec_full_reg_offset(s, a->rm),
+                           vsz, vsz, 0, gen_helper_sve2_rax1);
+    }
+    return true;
+}
-- 
2.17.1