Re: [PATCH for-5.1 3/7] hw/mips: Add CPU IRQ3 delivery for KVM

[Philippe Mathieu-Daudé]

On 4/27/20 11:33 AM, Huacai Chen wrote:
> Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add
> IP2 delivery as well, because Loongson-3 based machine use both IRQ2
> (CPU's IP2) and IRQ3 (CPU's IP3).
> 
> Signed-off-by: Huacai Chen <address@hidden>
> Co-developed-by: Jiaxun Yang <address@hidden>
> ---
>  hw/mips/mips_int.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
> index 796730b..5526219 100644
> --- a/hw/mips/mips_int.c
> +++ b/hw/mips/mips_int.c
> @@ -48,16 +48,14 @@ static void cpu_mips_irq_request(void *opaque, int irq, 
> int level)
>      if (level) {
>          env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
>  
> -        if (kvm_enabled() && irq == 2) {
> +        if (kvm_enabled() && (irq == 2 || irq == 3))

Shouldn't we check env->CP0_Config6 (or Config7) has the required
feature first?

>              kvm_mips_set_interrupt(cpu, irq, level);
> -        }
>  
>      } else {
>          env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
>  
> -        if (kvm_enabled() && irq == 2) {
> +        if (kvm_enabled() && (irq == 2 || irq == 3))
>              kvm_mips_set_interrupt(cpu, irq, level);
> -        }
>      }
>  
>      if (env->CP0_Cause & CP0Ca_IP_mask) {
>