[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 36/36] target/s390x: Use tcg_gen_gvec_rotl{i,s,v}
|
From: |
Richard Henderson |
|
Subject: |
[PATCH v2 36/36] target/s390x: Use tcg_gen_gvec_rotl{i,s,v} |
|
Date: |
Tue, 21 Apr 2020 18:17:22 -0700 |
Merge VERLL and VERLLV into op_vesv and op_ves, alongside
all of the other vector shift operations.
Cc: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/s390x/helper.h | 4 --
target/s390x/translate_vx.inc.c | 66 +++++----------------------------
target/s390x/vec_int_helper.c | 31 ----------------
target/s390x/insn-data.def | 4 +-
4 files changed, 11 insertions(+), 94 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index b5813c2ac2..b7887b552b 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -198,10 +198,6 @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void,
ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
-DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
-DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
-DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
-DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 12347f8a03..eb767f5288 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1825,63 +1825,6 @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps
*o)
return DISAS_NEXT;
}
-static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_i32 t0 = tcg_temp_new_i32();
-
- tcg_gen_andi_i32(t0, b, 31);
- tcg_gen_rotl_i32(d, a, t0);
- tcg_temp_free_i32(t0);
-}
-
-static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
-{
- TCGv_i64 t0 = tcg_temp_new_i64();
-
- tcg_gen_andi_i64(t0, b, 63);
- tcg_gen_rotl_i64(d, a, t0);
- tcg_temp_free_i64(t0);
-}
-
-static DisasJumpType op_verllv(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- static const GVecGen3 g[4] = {
- { .fno = gen_helper_gvec_verllv8, },
- { .fno = gen_helper_gvec_verllv16, },
- { .fni4 = gen_rll_i32, },
- { .fni8 = gen_rll_i64, },
- };
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec_3(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), &g[es]);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- static const GVecGen2s g[4] = {
- { .fno = gen_helper_gvec_verll8, },
- { .fno = gen_helper_gvec_verll16, },
- { .fni4 = gen_rll_i32, },
- { .fni8 = gen_rll_i64, },
- };
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
- gen_gvec_2s(get_field(s, v1), get_field(s, v3), o->addr1,
- &g[es]);
- return DISAS_NEXT;
-}
-
static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
{
TCGv_i32 t = tcg_temp_new_i32();
@@ -1946,6 +1889,9 @@ static DisasJumpType op_vesv(DisasContext *s, DisasOps *o)
case 0x70:
gen_gvec_fn_3(shlv, es, v1, v2, v3);
break;
+ case 0x73:
+ gen_gvec_fn_3(rotlv, es, v1, v2, v3);
+ break;
case 0x7a:
gen_gvec_fn_3(sarv, es, v1, v2, v3);
break;
@@ -1977,6 +1923,9 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
case 0x30:
gen_gvec_fn_2i(shli, es, v1, v3, d2);
break;
+ case 0x33:
+ gen_gvec_fn_2i(rotli, es, v1, v3, d2);
+ break;
case 0x3a:
gen_gvec_fn_2i(sari, es, v1, v3, d2);
break;
@@ -1994,6 +1943,9 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
case 0x30:
gen_gvec_fn_2s(shls, es, v1, v3, shift);
break;
+ case 0x33:
+ gen_gvec_fn_2s(rotls, es, v1, v3, shift);
+ break;
case 0x3a:
gen_gvec_fn_2s(sars, es, v1, v3, shift);
break;
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 0d6bc13dd6..5561b3ed90 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -515,37 +515,6 @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2,
uint32_t desc) \
DEF_VPOPCT(8)
DEF_VPOPCT(16)
-#define DEF_VERLLV(BITS)
\
-void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3,
\
- uint32_t desc)
\
-{
\
- int i;
\
-
\
- for (i = 0; i < (128 / BITS); i++) {
\
- const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i);
\
- const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i);
\
-
\
- s390_vec_write_element##BITS(v1, i, rol##BITS(a, b));
\
- }
\
-}
-DEF_VERLLV(8)
-DEF_VERLLV(16)
-
-#define DEF_VERLL(BITS)
\
-void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count,
\
- uint32_t desc)
\
-{
\
- int i;
\
-
\
- for (i = 0; i < (128 / BITS); i++) {
\
- const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i);
\
-
\
- s390_vec_write_element##BITS(v1, i, rol##BITS(a, count));
\
- }
\
-}
-DEF_VERLL(8)
-DEF_VERLL(16)
-
#define DEF_VERIM(BITS)
\
void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3,
\
uint32_t desc)
\
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 2bc77f0871..91ddaedd84 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1147,8 +1147,8 @@
/* VECTOR POPULATION COUNT */
F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC)
/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
- F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC)
- F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
+ F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
+ F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
/* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC)
/* VECTOR ELEMENT SHIFT LEFT */
--
2.20.1
- Re: [PATCH v2 27/36] tcg: Fix integral argument type to tcg_gen_rot[rl]i_i{32, 64}, (continued)
- [PATCH v2 28/36] tcg: Implement gvec support for rotate by immediate, Richard Henderson, 2020/04/21
- [PATCH v2 30/36] tcg: Remove expansion to shift by vector from do_shifts, Richard Henderson, 2020/04/21
- [PATCH v2 34/36] tcg/ppc: Implement INDEX_op_rot[lr]v_vec, Richard Henderson, 2020/04/21
- [PATCH v2 29/36] tcg: Implement gvec support for rotate by vector, Richard Henderson, 2020/04/21
- [PATCH v2 32/36] tcg/i386: Implement INDEX_op_rotl[is]_vec, Richard Henderson, 2020/04/21
- [PATCH v2 33/36] tcg/aarch64: Implement INDEX_op_rotli_vec, Richard Henderson, 2020/04/21
- [PATCH v2 36/36] target/s390x: Use tcg_gen_gvec_rotl{i,s,v},
Richard Henderson <=
- [PATCH v2 31/36] tcg: Implement gvec support for rotate by scalar, Richard Henderson, 2020/04/21
- [PATCH v2 35/36] target/ppc: Use tcg_gen_gvec_rotlv, Richard Henderson, 2020/04/21
- Re: [PATCH v2 00/36] tcg 5.1 omnibus patch set, Alex Bennée, 2020/04/23