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[PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine
From: |
Palmer Dabbelt |
Subject: |
[PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine |
Date: |
Tue, 21 Apr 2020 12:10:01 -0700 |
From: Bin Meng <address@hidden>
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-Id: <address@hidden>
[ Changed by AF:
- Use the SoC's serial property to pass the info to the SoC
- Fixup commit title
- Rebase on file restructuring
]
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 20 ++++++++++++++++++++
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9bfd16d2bb..eb0abcae89 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -34,6 +34,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
@@ -326,6 +327,8 @@ static void sifive_u_machine_init(MachineState *machine)
object_initialize_child(OBJECT(machine), "soc", &s->soc,
sizeof(s->soc), TYPE_RISCV_U_SOC,
&error_abort, NULL);
+ object_property_set_uint(OBJECT(&s->soc), s->serial, "serial",
+ &error_abort);
object_property_set_bool(OBJECT(&s->soc), true, "realized",
&error_abort);
@@ -417,6 +420,18 @@ static void sifive_u_machine_set_start_in_flash(Object
*obj, bool value, Error *
s->start_in_flash = value;
}
+static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char
*name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
+static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char
*name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
static void sifive_u_machine_instance_init(Object *obj)
{
SiFiveUState *s = RISCV_U_MACHINE(obj);
@@ -428,6 +443,11 @@ static void sifive_u_machine_instance_init(Object *obj)
"Set on to tell QEMU's ROM to jump to " \
"flash. Otherwise QEMU will jump to DRAM",
NULL);
+
+ s->serial = OTP_SERIAL;
+ object_property_add(obj, "serial", "uint32", sifive_u_machine_get_serial,
+ sifive_u_machine_set_serial, NULL, &s->serial, NULL);
+ object_property_set_description(obj, "serial", "Board serial number",
NULL);
}
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index a2baa1de5f..16c297ec5f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -61,6 +61,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+ uint32_t serial;
} SiFiveUState;
enum {
--
2.26.1.301.g55bc3eb7cb9-goog
- [PULL] RISC-V Patches for 5.0-rc4, Palmer Dabbelt, 2020/04/21
- [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs, Palmer Dabbelt, 2020/04/21
- [PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags, Palmer Dabbelt, 2020/04/21
- [PULL 4/6] riscv/sifive_u: Fix up file ordering, Palmer Dabbelt, 2020/04/21
- [PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine,
Palmer Dabbelt <=
- [PULL 3/6] riscv: AND stage-1 and stage-2 protection flags, Palmer Dabbelt, 2020/04/21
- [PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC, Palmer Dabbelt, 2020/04/21
- Re: [PULL] RISC-V Patches for 5.0-rc4, Peter Maydell, 2020/04/21