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Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u |
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Date: |
Mon, 20 Apr 2020 12:17:49 -0700 |
On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <address@hidden> wrote:
>
> On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <address@hidden> wrote:
> >
> > Hi Palmer,
> >
> > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> > <address@hidden> wrote:
> > >
> > > At present the board serial number is hard-coded to 1, and passed
> > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > > the serial number to generate a unique MAC address for the on-chip
> > > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > > created and connected to the same subnet, they all have the same
> > > MAC address hence it creates a unusable network.
> > >
> > > A new "serial" property is introduced to specify the board serial
> > > number. When not given, the default serial number 1 is used.
> > >
> >
> > Could you please take this for v5.0.0?
Applied to the RISC-V tree for 5.1
Alistair
>
> Ping?