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[PATCH v1 3/6] target/microblaze: Add the div-zero-exception property
From: |
Edgar E. Iglesias |
Subject: |
[PATCH v1 3/6] target/microblaze: Add the div-zero-exception property |
Date: |
Fri, 17 Apr 2020 21:10:19 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Add the div-zero-exception property to control if the core
traps divizions by zero.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/cpu.c | 2 ++
target/microblaze/cpu.h | 1 +
target/microblaze/op_helper.c | 5 +++--
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 36c20d9724..7a40e2fbad 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -280,6 +280,8 @@ static Property mb_properties[] = {
cfg.iopb_bus_exception, false),
DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
cfg.illegal_opcode_exception, false),
+ DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
+ cfg.div_zero_exception, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 71d7317a58..3c07f9b3f7 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -305,6 +305,7 @@ struct MicroBlazeCPU {
bool iopb_bus_exception;
bool illegal_opcode_exception;
bool opcode_0_illegal;
+ bool div_zero_exception;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index 18677ddfca..f3b17a95b3 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{
+ MicroBlazeCPU *cpu = env_archcpu(env);
+
if (b == 0) {
env->sregs[SR_MSR] |= MSR_DZ;
- if ((env->sregs[SR_MSR] & MSR_EE)
- && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
+ if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) {
env->sregs[SR_ESR] = ESR_EC_DIVZERO;
helper_raise_exception(env, EXCP_HW_EXCP);
}
--
2.20.1
- [PATCH v1 0/6] target-microblaze: Misc configurability #2, Edgar E. Iglesias, 2020/04/17
- [PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property, Edgar E. Iglesias, 2020/04/17
- [PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property, Edgar E. Iglesias, 2020/04/17
- [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property,
Edgar E. Iglesias <=
- [PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property, Edgar E. Iglesias, 2020/04/17
- [PATCH v1 5/6] target/microblaze: Add the pvr-user1 property, Edgar E. Iglesias, 2020/04/17
- [PATCH v1 6/6] target/microblaze: Add the pvr-user2 property, Edgar E. Iglesias, 2020/04/17