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[PULL 6/9] target/i386: Enable new apic id encoding for EPYC based cpus
From: |
Eduardo Habkost |
Subject: |
[PULL 6/9] target/i386: Enable new apic id encoding for EPYC based cpus models |
Date: |
Thu, 2 Apr 2020 19:20:48 -0300 |
From: Babu Moger <address@hidden>
The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
This works fine for most standard AMD and other vendors' configurations,
but this decoding sequence does not follow that of AMD's APIC ID enumeration
strictly. In some cases this can cause CPU topology inconsistency.
When booting a guest VM, the kernel tries to validate the topology, and finds
it inconsistent with the enumeration of EPYC cpu models. The more details are
in the bug https://bugzilla.redhat.com/show_bug.cgi?id=1728166.
To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors. The documentation is available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
It is also available at
https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
The new apic id encoding is enabled for EPYC and EPYC-Rome models.
Signed-off-by: Babu Moger <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
target/i386/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 50cd257a7e..468e03a153 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3925,6 +3925,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor",
.cache_info = &epyc_cache_info,
+ .use_epyc_apic_id_encoding = 1,
.versions = (X86CPUVersionDefinition[]) {
{ .version = 1 },
{
@@ -4052,6 +4053,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "AMD EPYC-Rome Processor",
.cache_info = &epyc_rome_cache_info,
+ .use_epyc_apic_id_encoding = 1,
},
};
--
2.24.1
- [PULL 0/9] x86 queue for -rc2, Eduardo Habkost, 2020/04/02
- [PULL 2/9] target/i386: Cleanup and use the EPYC mode topology functions, Eduardo Habkost, 2020/04/02
- [PULL 1/9] hw/386: Add EPYC mode topology decoding functions, Eduardo Habkost, 2020/04/02
- [PULL 3/9] hw/i386: Introduce apicid functions inside X86MachineState, Eduardo Habkost, 2020/04/02
- [PULL 4/9] i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition, Eduardo Habkost, 2020/04/02
- [PULL 5/9] hw/i386: Move arch_id decode inside x86_cpus_init, Eduardo Habkost, 2020/04/02
- [PULL 7/9] i386: Fix pkg_id offset for EPYC cpu models, Eduardo Habkost, 2020/04/02
- [PULL 8/9] target/i386: set the CPUID level to 0x14 on old machine-type, Eduardo Habkost, 2020/04/02
- [PULL 6/9] target/i386: Enable new apic id encoding for EPYC based cpus models,
Eduardo Habkost <=
- [PULL 9/9] target/i386: Add ARCH_CAPABILITIES related bits into Icelake-Server CPU model, Eduardo Habkost, 2020/04/02
- Re: [PULL 0/9] x86 queue for -rc2, Peter Maydell, 2020/04/03