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[PATCH v2 12/22] intel_iommu: process PASID cache invalidation
From: |
Liu Yi L |
Subject: |
[PATCH v2 12/22] intel_iommu: process PASID cache invalidation |
Date: |
Sun, 29 Mar 2020 21:24:51 -0700 |
This patch adds PASID cache invalidation handling. When guest enabled
PASID usages (e.g. SVA), guest software should issue a proper PASID
cache invalidation when caching-mode is exposed. This patch only adds
the draft handling of pasid cache invalidation. Detailed handling will
be added in subsequent patches.
v1 -> v2: remove vtd_pasid_cache_gsi(), vtd_pasid_cache_psi() and
vtd_pasid_cache_dsi()
Cc: Kevin Tian <address@hidden>
Cc: Jacob Pan <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: Yi Sun <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Signed-off-by: Liu Yi L <address@hidden>
---
hw/i386/intel_iommu.c | 40 +++++++++++++++++++++++++++++++++++-----
hw/i386/intel_iommu_internal.h | 12 ++++++++++++
hw/i386/trace-events | 3 +++
3 files changed, 50 insertions(+), 5 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 6c3159f..2eb60c3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2395,6 +2395,37 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
return true;
}
+static bool vtd_process_pasid_desc(IntelIOMMUState *s,
+ VTDInvDesc *inv_desc)
+{
+ if ((inv_desc->val[0] & VTD_INV_DESC_PASIDC_RSVD_VAL0) ||
+ (inv_desc->val[1] & VTD_INV_DESC_PASIDC_RSVD_VAL1) ||
+ (inv_desc->val[2] & VTD_INV_DESC_PASIDC_RSVD_VAL2) ||
+ (inv_desc->val[3] & VTD_INV_DESC_PASIDC_RSVD_VAL3)) {
+ error_report_once("non-zero-field-in-pc_inv_desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+
+ switch (inv_desc->val[0] & VTD_INV_DESC_PASIDC_G) {
+ case VTD_INV_DESC_PASIDC_DSI:
+ break;
+
+ case VTD_INV_DESC_PASIDC_PASID_SI:
+ break;
+
+ case VTD_INV_DESC_PASIDC_GLOBAL:
+ break;
+
+ default:
+ error_report_once("invalid-inv-granu-in-pc_inv_desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+
+ return true;
+}
+
static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
@@ -2501,12 +2532,11 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
}
break;
- /*
- * TODO: the entity of below two cases will be implemented in future
series.
- * To make guest (which integrates scalable mode support patch set in
- * iommu driver) work, just return true is enough so far.
- */
case VTD_INV_DESC_PC:
+ trace_vtd_inv_desc("pasid-cache", inv_desc.val[1], inv_desc.val[0]);
+ if (!vtd_process_pasid_desc(s, &inv_desc)) {
+ return false;
+ }
break;
case VTD_INV_DESC_PIOTLB:
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 3fc83f1..9a76f20 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -444,6 +444,18 @@ typedef union VTDInvDesc VTDInvDesc;
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
+#define VTD_INV_DESC_PASIDC_G (3ULL << 4)
+#define VTD_INV_DESC_PASIDC_PASID(val) (((val) >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PASIDC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
+#define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000ffc0ULL
+#define VTD_INV_DESC_PASIDC_RSVD_VAL1 0xffffffffffffffffULL
+#define VTD_INV_DESC_PASIDC_RSVD_VAL2 0xffffffffffffffffULL
+#define VTD_INV_DESC_PASIDC_RSVD_VAL3 0xffffffffffffffffULL
+
+#define VTD_INV_DESC_PASIDC_DSI (0ULL << 4)
+#define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4)
+#define VTD_INV_DESC_PASIDC_GLOBAL (3ULL << 4)
+
/* Information about page-selective IOTLB invalidate */
struct VTDIOTLBPageInvInfo {
uint16_t domain_id;
diff --git a/hw/i386/trace-events b/hw/i386/trace-events
index 71536a7..f7cd4e5 100644
--- a/hw/i386/trace-events
+++ b/hw/i386/trace-events
@@ -22,6 +22,9 @@ vtd_inv_qi_head(uint16_t head) "read head %d"
vtd_inv_qi_tail(uint16_t head) "write tail %d"
vtd_inv_qi_fetch(void) ""
vtd_context_cache_reset(void) ""
+vtd_pasid_cache_gsi(void) ""
+vtd_pasid_cache_dsi(uint16_t domain) "Domian slective PC invalidation domain
0x%"PRIx16
+vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID slective PC
invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32
vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present"
vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"
devfn %"PRIu8" not present"
vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t
domain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64"
domain 0x%"PRIx16
--
2.7.4
- [PATCH v2 04/22] hw/iommu: introduce HostIOMMUContext, (continued)
- [PATCH v2 04/22] hw/iommu: introduce HostIOMMUContext, Liu Yi L, 2020/03/30
- [PATCH v2 06/22] hw/pci: introduce pci_device_set/unset_iommu_context(), Liu Yi L, 2020/03/30
- [PATCH v2 10/22] vfio/pci: set host iommu context to vIOMMU, Liu Yi L, 2020/03/30
- [PATCH v2 07/22] intel_iommu: add set/unset_iommu_context callback, Liu Yi L, 2020/03/30
- [PATCH v2 22/22] intel_iommu: modify x-scalable-mode to be string option, Liu Yi L, 2020/03/30
- [PATCH v2 09/22] vfio/common: init HostIOMMUContext per-container, Liu Yi L, 2020/03/30
- [PATCH v2 02/22] header file update VFIO/IOMMU vSVA APIs, Liu Yi L, 2020/03/30
- [PATCH v2 08/22] vfio/common: provide PASID alloc/free hooks, Liu Yi L, 2020/03/30
- [PATCH v2 05/22] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps, Liu Yi L, 2020/03/30
- [PATCH v2 12/22] intel_iommu: process PASID cache invalidation,
Liu Yi L <=
- [PATCH v2 11/22] intel_iommu: add virtual command capability support, Liu Yi L, 2020/03/30
- [PATCH v2 13/22] intel_iommu: add PASID cache management infrastructure, Liu Yi L, 2020/03/30
- [PATCH v2 16/22] intel_iommu: replay pasid binds after context cache invalidation, Liu Yi L, 2020/03/30
- [PATCH v2 15/22] intel_iommu: bind/unbind guest page table to host, Liu Yi L, 2020/03/30
- [PATCH v2 14/22] vfio: add bind stage-1 page table support, Liu Yi L, 2020/03/30
- [PATCH v2 19/22] intel_iommu: process PASID-based iotlb invalidation, Liu Yi L, 2020/03/30
- [PATCH v2 17/22] intel_iommu: do not pass down pasid bind for PASID #0, Liu Yi L, 2020/03/30
- [PATCH v2 18/22] vfio: add support for flush iommu stage-1 cache, Liu Yi L, 2020/03/30
- [PATCH v2 21/22] intel_iommu: process PASID-based Device-TLB invalidation, Liu Yi L, 2020/03/30
- [PATCH v2 20/22] intel_iommu: propagate PASID-based iotlb invalidation to host, Liu Yi L, 2020/03/30