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Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply


From: Richard Henderson
Subject: Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions
Date: Sat, 28 Mar 2020 08:47:29 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1

On 3/28/20 8:17 AM, LIU Zhiwei wrote:
>> Missed the improvement here.  See tcg_gen_mulsu2_i64.
> Though I have not gotten the principle, the code in tcg_gen_mulsu2_i64 is much
> tidier.

Let A = signed operand,
    B = unsigned operand
    P = unsigned product

If the sign bit A is set, then P is too large.
In that case we subtract 2**64 * B to fix that:

    HI_P -= (A < 0 ? B : 0)

where the conditional is computed as (A >> 63) & B.


r~



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