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Re: [PATCH v6 61/61] target/riscv: configure and turn on vector extensio
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line |
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Date: |
Fri, 27 Mar 2020 21:00:49 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
> Vector extension is default off. The only way to use vector extension is
> 1. use cpu rv32 or rv64
> 2. turn on it by command line
> "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1".
>
> vlen is the vector register length, default value is 128 bit.
> elen is the max operator size in bits, default value is 64 bit.
> vext_spec is the vector specification version, default value is v0.7.1.
> These properties can be specified with other values.
>
> Signed-off-by: LIU Zhiwei <address@hidden>
> ---
> target/riscv/cpu.c | 44 +++++++++++++++++++++++++++++++++++++++++++-
> target/riscv/cpu.h | 2 ++
> 2 files changed, 45 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [PATCH v6 56/61] target/riscv: integer scalar move instruction, (continued)
- [PATCH v6 56/61] target/riscv: integer scalar move instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 57/61] target/riscv: floating-point scalar move instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 58/61] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 59/61] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 60/61] target/riscv: vector compress instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line, LIU Zhiwei, 2020/03/17
- Re: [PATCH v6 00/61] target/riscv: support vector extension v0.7.1, no-reply, 2020/03/17