[PATCH 1/3] target/mips: Introduce loongson ext & mmi ASE flags

[Jiaxun Yang]

Start from Loongson-3A, loongson treat their extension instructions
as ASE and implemented mips64r2 as their baseline ISA.
Here we simply identify instructions shared between 2F and 3A and
mark them with MMI or EXT flag.

Signed-off-by: Jiaxun Yang <address@hidden>
---
 target/mips/mips-defs.h | 2 ++
 target/mips/translate.c | 9 +++++----
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index a831bb4384..1d25417c76 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -58,6 +58,8 @@
  */
 #define ASE_MMI           0x0100000000000000ULL
 #define ASE_MXU           0x0200000000000000ULL
+#define ASE_LOONGSON_MMI  0x0400000000000000ULL
+#define ASE_LOONGSON_EXT  0x0800000000000000ULL
 
 /* MIPS CPU defines. */
 #define CPU_MIPS1       (ISA_MIPS1)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 25b595a17d..2d556e0dea 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3421,7 +3421,8 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
     TCGv t0, t1, t2;
     int mem_idx = ctx->mem_idx;
 
-    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
+    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
+                                        ASE_LOONGSON_EXT)) {
         /*
          * Loongson CPU uses a load to zero register for prefetch.
          * We emulate it as a NOP. On other CPU we must perform the
@@ -27161,7 +27162,7 @@ static void decode_opc_special2_legacy(CPUMIPSState 
*env, DisasContext *ctx)
     case OPC_MULTU_G_2F:
     case OPC_MOD_G_2F:
     case OPC_MODU_G_2F:
-        check_insn(ctx, INSN_LOONGSON2F);
+        check_insn(ctx, INSN_LOONGSON2F | ASE_LOONGSON_EXT);
         gen_loongson_integer(ctx, op1, rd, rs, rt);
         break;
     case OPC_CLO:
@@ -27194,7 +27195,7 @@ static void decode_opc_special2_legacy(CPUMIPSState 
*env, DisasContext *ctx)
     case OPC_DDIVU_G_2F:
     case OPC_DMOD_G_2F:
     case OPC_DMODU_G_2F:
-        check_insn(ctx, INSN_LOONGSON2F);
+        check_insn(ctx, INSN_LOONGSON2F | ASE_LOONGSON_EXT);
         gen_loongson_integer(ctx, op1, rd, rs, rt);
         break;
 #endif
@@ -30641,7 +30642,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext 
*ctx)
         }
         break;
     case OPC_CP2:
-        check_insn(ctx, INSN_LOONGSON2F);
+        check_insn(ctx, INSN_LOONGSON2F | ASE_LOONGSON_MMI);
         /* Note that these instructions use different fields.  */
         gen_loongson_multimedia(ctx, sa, rd, rt);
         break;
-- 
2.26.0.rc2