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Re: [PATCH v5 57/60] target/riscv: vector slide instructions
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v5 57/60] target/riscv: vector slide instructions |
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Date: |
Tue, 24 Mar 2020 07:52:06 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/24/20 3:51 AM, LIU Zhiwei wrote:
>> (3) It would be handy to have TCGv cpu_vl.
> Do you mean I should define cpu_vl as a global TCG varible like cpu_pc?
> So that I can check vl==0 in translation time.
Yes.
>> vslide1up.vx:
>> Ho hum, I forgot about masking. Some options:
>> (1) Call a helper just as you did in your original patch.
>> (2) Call a helper only for !vm, for vm as below.
>
> Sorry, I don't get it why I need a helper for !vm.
> I think I can call vslideup w/1 whether !vm or vm, then a store to vd[0].
That's right. I didn't mean a helper specific to vslide1up, but any helper.
r~
- Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructions, (continued)
[PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 58/60] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/03/12
[PATCH v5 59/60] target/riscv: vector compress instruction, LIU Zhiwei, 2020/03/12
[PATCH v5 60/60] target/riscv: configure and turn on vector extension from command line, LIU Zhiwei, 2020/03/12
Re: [PATCH v5 00/60] target/riscv: support vector extension v0.7.1, no-reply, 2020/03/12
Re: [PATCH v5 35/60] target/riscv: vector floating-point square-root instruction, Richard Henderson, 2020/03/15
Re: [PATCH v5 51/60] target/riscv: set-X-first mask bit, Richard Henderson, 2020/03/15
Re: [PATCH v5 59/60] target/riscv: vector compress instruction, Richard Henderson, 2020/03/15