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Re: [PATCH v5 22/60] target/riscv: vector integer merge and move instruc
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v5 22/60] target/riscv: vector integer merge and move instructions |
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Date: |
Sat, 14 Mar 2020 00:27:55 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* Vector Integer Merge and Move Instructions */
> +static bool opivv_vmerge_check(DisasContext *s, arg_rmrr *a)
> +{
> + return (vext_check_isa_ill(s, RVV) &&
> + vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> + vext_check_reg(s, a->rd, false) &&
> + vext_check_reg(s, a->rs2, false) &&
> + vext_check_reg(s, a->rs1, false) &&
> + ((a->vm == 0) || (a->rs2 == 0)));
> +}
> +GEN_OPIVV_TRANS(vmerge_vvm, opivv_vmerge_check)
> +
> +static bool opivx_vmerge_check(DisasContext *s, arg_rmrr *a)
> +{
> + return (vext_check_isa_ill(s, RVV) &&
> + vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> + vext_check_reg(s, a->rd, false) &&
> + vext_check_reg(s, a->rs2, false) &&
> + ((a->vm == 0) || (a->rs2 == 0)));
> +}
> +GEN_OPIVX_TRANS(vmerge_vxm, opivx_vmerge_check)
> +
> +GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vmerge_check)
I think you need to special case these. The unmasked instructions are the
canonical move instructions: vmv.v.*.
You definitely want to use tcg_gen_gvec_mov (vv), tcg_gen_gvec_dup_i{32,64}
(vx) and tcg_gen_gvec_dup{8,16,32,64}i (vi).
> + if (!vm && !vext_elem_mask(v0, mlen, i)) { \
> + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> + *((ETYPE *)vd + H1(i)) = s2; \
> + } else { \
> + ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
> + *((ETYPE *)vd + H(i)) = s1; \
> + } \
Perhaps better as
ETYPE *vt = (!vm && !vext_elem_mask(v0, mlen, i) ? vs2 : vs1);
*((ETYPE *)vd + H(i)) = *((ETYPE *)vt + H(i));
> + if (!vm && !vext_elem_mask(v0, mlen, i)) { \
> + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> + *((ETYPE *)vd + H1(i)) = s2; \
> + } else { \
> + *((ETYPE *)vd + H(i)) = (ETYPE)(target_long)s1; \
> + } \
Perhaps better as
ETYPE s2 = *((ETYPE *)vs2 + H(i));
ETYPE d = (!vm && !vext_elem_mask(v0, mlen, i)
? s2 : (ETYPE)(target_long)s1);
*((ETYPE *)vd + H(i)) = d;
as most host platforms have a conditional reg-reg move, but not a conditional
load.
r~
- Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions, (continued)
- [PATCH v5 18/60] target/riscv: vector integer divide instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 19/60] target/riscv: vector widening integer multiply instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 20/60] target/riscv: vector single-width integer multiply-add instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 21/60] target/riscv: vector widening integer multiply-add instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 22/60] target/riscv: vector integer merge and move instructions, LIU Zhiwei, 2020/03/12
- Re: [PATCH v5 22/60] target/riscv: vector integer merge and move instructions,
Richard Henderson <=
- [PATCH v5 23/60] target/riscv: vector single-width saturating add and subtract, LIU Zhiwei, 2020/03/12
- [PATCH v5 24/60] target/riscv: vector single-width averaging add and subtract, LIU Zhiwei, 2020/03/12