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Re: [PATCH v5 06/60] target/riscv: add vector index load and store instr
From: |
Richard Henderson |
Subject: |
Re: [PATCH v5 06/60] target/riscv: add vector index load and store instructions |
Date: |
Fri, 13 Mar 2020 18:49:38 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static inline void vext_ldst_index(void *vd, void *v0, target_ulong base,
> + void *vs2, CPURISCVState *env, uint32_t desc,
> + vext_get_index_addr get_index_addr,
> + vext_ldst_elem_fn ldst_elem,
> + vext_ld_clear_elem clear_elem,
> + uint32_t esz, uint32_t msz, uintptr_t ra,
> + MMUAccessType access_type)
> +{
> + uint32_t i, k;
> + uint32_t nf = vext_nf(desc);
> + uint32_t vm = vext_vm(desc);
> + uint32_t mlen = vext_mlen(desc);
> + uint32_t vlmax = vext_maxsz(desc) / esz;
> +
> + if (env->vl == 0) {
> + return;
> + }
> + /* probe every access*/
> + for (i = 0; i < env->vl; i++) {
> + if (!vm && !vext_elem_mask(v0, mlen, i)) {
> + continue;
> + }
> + probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
> + access_type);
Indentation.
> + /* load bytes from guest memory */
> + for (i = 0; i < env->vl; i++) {
> + k = 0;
> + if (!vm && !vext_elem_mask(v0, mlen, i)) {
> + continue;
> + }
> + while (k < nf) {
> + abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
> + ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + k++;
> + }
Why the odd formulation with k?
> + for (k = 0; k < nf; k++) {
> + clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
> + }
Using a for is certainly a bit clearer.
Which does bring to mind an optimization -- letting the compiler know that
these loops always go at least once.
We can do that either by writing all of them as do { } while.
Or by encoding NF in desc like the instruction does:
static inline uint32_t vext_nf(uint32_t desc)
{
return FIELD_EX32(simd_data(desc), VDATA, NF) + 1;
}
which will let the compiler know that NF >= 1.
But that's minor, and we can look at these sorts of things later.
Reviewed-by: Richard Henderson <address@hidden>
r~
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions, Richard Henderson, 2020/03/13
[PATCH v5 06/60] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 07/60] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/03/12
[PATCH v5 08/60] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/12
[PATCH v5 09/60] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/03/12