Re: [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR maski

qemu-devel

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR maski

From:	David Gibson
Subject:	Re: [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR masking
Date:	Wed, 11 Mar 2020 14:15:09 +1100

On Tue, Mar 10, 2020 at 11:06:08AM +0100, Cédric Le Goater wrote:
> On 3/3/20 4:43 AM, David Gibson wrote:
> > When we store the Logical Partitioning Control Register (LPCR) we have a
> > big switch statement to work out which are valid bits for the cpu model
> > we're emulating.
> > 
> > As well as being ugly, this isn't really conceptually correct, since it is
> > based on the mmu_model variable, whereas the LPCR isn't (only) about the
> > MMU, so mmu_model is basically just acting as a proxy for the cpu model.
> > 
> > Handle this in a simpler way, by adding a suitable lpcr_mask to the QOM
> > class.
> > 
> > Signed-off-by: David Gibson <address@hidden>
> > Reviewed-by: Cédric Le Goater <address@hidden>
> > Reviewed-by: Greg Kurz <address@hidden>
> > ---
> >  target/ppc/cpu-qom.h            |  1 +
> >  target/ppc/mmu-hash64.c         | 36 ++-------------------------------
> >  target/ppc/translate_init.inc.c | 27 +++++++++++++++++++++----
> >  3 files changed, 26 insertions(+), 38 deletions(-)
> > 
> > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> > index e499575dc8..15d6b54a7d 100644
> > --- a/target/ppc/cpu-qom.h
> > +++ b/target/ppc/cpu-qom.h
> > @@ -177,6 +177,7 @@ typedef struct PowerPCCPUClass {
> >      uint64_t insns_flags;
> >      uint64_t insns_flags2;
> >      uint64_t msr_mask;
> > +    uint64_t lpcr_mask;         /* Available bits in the LPCR */
> >      uint64_t lpcr_pm;           /* Power-saving mode Exit Cause Enable 
> > bits */
> >      powerpc_mmu_t   mmu_model;
> >      powerpc_excp_t  excp_model;
> > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> > index caf47ad6fc..0ef330a614 100644
> > --- a/target/ppc/mmu-hash64.c
> > +++ b/target/ppc/mmu-hash64.c
> > @@ -1095,42 +1095,10 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu)
> >  
> >  void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
> >  {
> > +    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> >      CPUPPCState *env = &cpu->env;
> > -    uint64_t lpcr = 0;
> >  
> > -    /* Filter out bits */
> > -    switch (env->mmu_model) {
> > -    case POWERPC_MMU_2_03: /* P5p */
> > -        lpcr = val & (LPCR_RMLS | LPCR_ILE |
> > -                      LPCR_LPES0 | LPCR_LPES1 |
> > -                      LPCR_RMI | LPCR_HDICE);
> > -        break;
> > -    case POWERPC_MMU_2_06: /* P7 */
> > -        lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
> > -                      LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> > -                      LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
> > -                      LPCR_MER | LPCR_TC |
> > -                      LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
> > -        break;
> > -    case POWERPC_MMU_2_07: /* P8 */
> > -        lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
> > -                      LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> > -                      LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
> > -                      LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
> > -                      LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
> > -        break;
> > -    case POWERPC_MMU_3_00: /* P9 */
> > -        lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> > -                      (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL 
> > |
> > -                      LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | 
> > LPCR_LD |
> > -                      (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | 
> > LPCR_EEE |
> > -                      LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | 
> > LPCR_TC |
> > -                      LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
> > -        break;
> > -    default:
> > -        g_assert_not_reached();
> > -    }
> > -    env->spr[SPR_LPCR] = lpcr;
> > +    env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
> >      ppc_hash64_update_rmls(cpu);
> >      ppc_hash64_update_vrma(cpu);
> >  }
> > diff --git a/target/ppc/translate_init.inc.c 
> > b/target/ppc/translate_init.inc.c
> > index f7acd3d61d..68aa4dfad8 100644
> > --- a/target/ppc/translate_init.inc.c
> > +++ b/target/ppc/translate_init.inc.c
> > @@ -8476,6 +8476,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> >                      (1ull << MSR_DR) |
> >                      (1ull << MSR_PMM) |
> >                      (1ull << MSR_RI);
> > +    pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
> > +        LPCR_RMI | LPCR_HDICE;
> >      pcc->mmu_model = POWERPC_MMU_2_03;
> >  #if defined(CONFIG_SOFTMMU)
> >      pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> > @@ -8614,6 +8616,12 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> >                      (1ull << MSR_PMM) |
> >                      (1ull << MSR_RI) |
> >                      (1ull << MSR_LE);
> > +    pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
> > +        LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> > +        LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
> > +        LPCR_MER | LPCR_TC |
> > +        LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
> > +    pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
> >      pcc->mmu_model = POWERPC_MMU_2_06;
> >  #if defined(CONFIG_SOFTMMU)
> >      pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> > @@ -8630,7 +8638,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> >      pcc->l1_dcache_size = 0x8000;
> >      pcc->l1_icache_size = 0x8000;
> >      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> > -    pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
> >  }
> >  
> >  static void init_proc_POWER8(CPUPPCState *env)
> > @@ -8785,6 +8792,13 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >                      (1ull << MSR_TS0) |
> >                      (1ull << MSR_TS1) |
> >                      (1ull << MSR_LE);
> > +    pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
> > +        LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
> > +        LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
> > +        LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
> > +        LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
> > +    pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
> > +                   LPCR_P8_PECE3 | LPCR_P8_PECE4;
> >      pcc->mmu_model = POWERPC_MMU_2_07;
> >  #if defined(CONFIG_SOFTMMU)
> >      pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> > @@ -8802,8 +8816,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >      pcc->l1_dcache_size = 0x8000;
> >      pcc->l1_icache_size = 0x8000;
> >      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> > -    pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
> > -                   LPCR_P8_PECE3 | LPCR_P8_PECE4;
> >  }
> >  
> >  #ifdef CONFIG_SOFTMMU
> > @@ -8995,6 +9007,14 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> >                      (1ull << MSR_PMM) |
> >                      (1ull << MSR_RI) |
> >                      (1ull << MSR_LE);
> > +    pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> > +        (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> > +        LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
> > +        (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
> > +                             LPCR_DEE | LPCR_OEE))
> > +        | LPCR_MER | LPCR_GTSE | LPCR_TC |
> > +        LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
> > +    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
> >      pcc->mmu_model = POWERPC_MMU_3_00;
> >  #if defined(CONFIG_SOFTMMU)
> >      pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
> > @@ -9014,7 +9034,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> >      pcc->l1_dcache_size = 0x8000;
> >      pcc->l1_icache_size = 0x8000;
> >      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> > -    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
> >  }
> >  
> >  #ifdef CONFIG_SOFTMMU
> > 
> 
> David,
> 
> We forgot the POWER10 CPU. Could you squeeze the changes below in that 
> patch ?

Oops, I thought I'd covered that, but apparently not.

I've squashed this into the original patch.


> 
> Thanks,
> 
> C. 
> 
> >From a0d8cbc786c16b73376642f632cba99d75783da7 Mon Sep 17 00:00:00 2001
> From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <address@hidden>
> Date: Tue, 10 Mar 2020 11:02:40 +0100
> Subject: [PATCH] target/ppc: Add a LPCR mask to POWER10 CPU
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
> 
> Fixes: 2d21e1e2a35c ("target/ppc: Use class fields to simplify LPCR masking")
> Signed-off-by: Cédric Le Goater <address@hidden>
> ---
>  target/ppc/translate_init.inc.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 68aa4dfad875..0ae145e18d80 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -9224,6 +9224,14 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>                      (1ull << MSR_PMM) |
>                      (1ull << MSR_RI) |
>                      (1ull << MSR_LE);
> +    pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> +        (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> +        LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
> +        (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
> +                             LPCR_DEE | LPCR_OEE))
> +        | LPCR_MER | LPCR_GTSE | LPCR_TC |
> +        LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
> +    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
>      pcc->mmu_model = POWERPC_MMU_3_00;
>  #if defined(CONFIG_SOFTMMU)
>      pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
> @@ -9242,7 +9250,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>      pcc->l1_dcache_size = 0x8000;
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> -    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
>  }
>  
>  #if !defined(CONFIG_USER_ONLY)

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

signature.asc
Description: PGP signature

[Prev in Thread]

Current Thread

[Next in Thread]

Re: [PATCH v7 11/17] target/ppc: Don't store VRMA SLBE persistently, (continued)
- [PATCH v7 16/17] spapr: Clean up RMA size calculation, David Gibson, 2020/03/02
  - Re: [PATCH v7 16/17] spapr: Clean up RMA size calculation, Greg Kurz, 2020/03/03
  - Re: [PATCH v7 16/17] spapr: Clean up RMA size calculation, Philippe Mathieu-Daudé, 2020/03/05
- [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR masking, David Gibson, 2020/03/02
  - Re: [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR masking, Philippe Mathieu-Daudé, 2020/03/05
  - Re: [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR masking, Cédric Le Goater, 2020/03/10
    - Re: [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR masking, David Gibson <=
- [PATCH v7 17/17] spapr: Fold spapr_node0_size() into its only caller, David Gibson, 2020/03/02
  - Re: [PATCH v7 17/17] spapr: Fold spapr_node0_size() into its only caller, Greg Kurz, 2020/03/03
    - Re: [PATCH v7 17/17] spapr: Fold spapr_node0_size() into its only caller, David Gibson, 2020/03/03
- [PATCH v7 10/17] target/ppc: Only calculate RMLS derived RMA limit on demand, David Gibson, 2020/03/02
  - Re: [PATCH v7 10/17] target/ppc: Only calculate RMLS derived RMA limit on demand, Greg Kurz, 2020/03/03
  - Re: [PATCH v7 10/17] target/ppc: Only calculate RMLS derived RMA limit on demand, Philippe Mathieu-Daudé, 2020/03/05
- [PATCH v7 12/17] spapr: Don't use weird units for MIN_RMA_SLOF, David Gibson, 2020/03/02
  - Re: [PATCH v7 12/17] spapr: Don't use weird units for MIN_RMA_SLOF, Philippe Mathieu-Daudé, 2020/03/05
- [PATCH v7 15/17] spapr: Don't clamp RMA to 16GiB on new machine types, David Gibson, 2020/03/02
  - Re: [PATCH v7 15/17] spapr: Don't clamp RMA to 16GiB on new machine types, Greg Kurz, 2020/03/03

Prev by Date: [PATCH v3] block/iscsi:use the flags in iscsi_open() prevent Clang warning
Next by Date: Re: [PATCH qemu v8 1/3] ppc/spapr: Move GPRs setup to one place
Previous by thread: Re: [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR masking
Next by thread: [PATCH v7 17/17] spapr: Fold spapr_node0_size() into its only caller
Index(es):
- Date
- Thread