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[PULL 01/37] hw/arm: versal: Add support for the LPD ADMAs
From: |
Peter Maydell |
Subject: |
[PULL 01/37] hw/arm: versal: Add support for the LPD ADMAs |
Date: |
Thu, 5 Mar 2020 16:30:24 +0000 |
From: "Edgar E. Iglesias" <address@hidden>
Add support for the Versal LPD ADMAs.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/arm/xlnx-versal.h | 6 ++++++
hw/arm/xlnx-versal.c | 24 ++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index d844c4ffe47..6c0a692b2fd 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -22,6 +22,7 @@
#define XLNX_VERSAL_NR_ACPUS 2
#define XLNX_VERSAL_NR_UARTS 2
#define XLNX_VERSAL_NR_GEMS 2
+#define XLNX_VERSAL_NR_ADMAS 8
#define XLNX_VERSAL_NR_IRQS 192
typedef struct Versal {
@@ -50,6 +51,7 @@ typedef struct Versal {
struct {
SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
+ SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
} iou;
} lpd;
@@ -74,6 +76,7 @@ typedef struct Versal {
#define VERSAL_GEM0_WAKE_IRQ_0 57
#define VERSAL_GEM1_IRQ_0 58
#define VERSAL_GEM1_WAKE_IRQ_0 59
+#define VERSAL_ADMA_IRQ_0 60
/* Architecturally reserved IRQs suitable for virtualization. */
#define VERSAL_RSVD_IRQ_FIRST 111
@@ -96,6 +99,9 @@ typedef struct Versal {
#define MM_GEM1 0xff0d0000U
#define MM_GEM1_SIZE 0x10000
+#define MM_ADMA_CH0 0xffa80000U
+#define MM_ADMA_CH0_SIZE 0x10000
+
#define MM_OCM 0xfffc0000U
#define MM_OCM_SIZE 0x40000
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 403fc7b8814..cb0122a3a68 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -194,6 +194,29 @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
}
}
+static void versal_create_admas(Versal *s, qemu_irq *pic)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
+ char *name = g_strdup_printf("adma%d", i);
+ DeviceState *dev;
+ MemoryRegion *mr;
+
+ dev = qdev_create(NULL, "xlnx.zdma");
+ s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev);
+ object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
+ qdev_init_nofail(dev);
+
+ mr = sysbus_mmio_get_region(s->lpd.iou.adma[i], 0);
+ memory_region_add_subregion(&s->mr_ps,
+ MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
+
+ sysbus_connect_irq(s->lpd.iou.adma[i], 0, pic[VERSAL_ADMA_IRQ_0 + i]);
+ g_free(name);
+ }
+}
+
/* This takes the board allocated linear DDR memory and creates aliases
* for each split DDR range/aperture on the Versal address map.
*/
@@ -275,6 +298,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_apu_gic(s, pic);
versal_create_uarts(s, pic);
versal_create_gems(s, pic);
+ versal_create_admas(s, pic);
versal_map_ddr(s);
versal_unimp(s);
--
2.20.1
- [PULL 26/37] tests/tcg/aarch64: Add newline in pauth-1 printf, (continued)
- [PULL 26/37] tests/tcg/aarch64: Add newline in pauth-1 printf, Peter Maydell, 2020/03/05
- [PULL 34/37] target/arm: Apply TBI to ESR_ELx in helper_exception_return, Peter Maydell, 2020/03/05
- [PULL 36/37] target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva, Peter Maydell, 2020/03/05
- [PULL 31/37] target/arm: Replicate TBI/TBID bits for single range regimes, Peter Maydell, 2020/03/05
- [PULL 32/37] target/arm: Optimize cpu_mmu_index, Peter Maydell, 2020/03/05
- [PULL 33/37] target/arm: Introduce core_to_aa64_mmu_idx, Peter Maydell, 2020/03/05
- [PULL 20/37] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Peter Maydell, 2020/03/05
- [PULL 23/37] target/arm: Honor the HCR_EL2.TPCP bit, Peter Maydell, 2020/03/05
- [PULL 37/37] target/arm: Clean address for DC ZVA, Peter Maydell, 2020/03/05
- [PULL 35/37] target/arm: Move helper_dc_zva to helper-a64.c, Peter Maydell, 2020/03/05
- [PULL 01/37] hw/arm: versal: Add support for the LPD ADMAs,
Peter Maydell <=
- [PULL 07/37] hw/arm/mainstone: Simplify since the machines are little-endian only, Peter Maydell, 2020/03/05
- [PULL 13/37] hw/arm/strongarm: move timer_new from init() into realize() to avoid memleaks, Peter Maydell, 2020/03/05
- [PULL 12/37] hw/arm/spitz: move timer_new from init() into realize() to avoid memleaks, Peter Maydell, 2020/03/05
- [PULL 14/37] hw/timer/cadence_ttc: move timer_new from init() into realize() to avoid memleaks, Peter Maydell, 2020/03/05
- [PULL 17/37] target/arm: Disable has_el2 and has_el3 for user-only, Peter Maydell, 2020/03/05
- [PULL 19/37] target/arm: Improve masking in arm_hcr_el2_eff, Peter Maydell, 2020/03/05
- [PULL 28/37] hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8, Peter Maydell, 2020/03/05
- Re: [PULL 00/37] target-arm queue, Peter Maydell, 2020/03/05