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[PULL 04/33] arm_gic: Mask the un-supported priority bits
From: |
Peter Maydell |
Subject: |
[PULL 04/33] arm_gic: Mask the un-supported priority bits |
Date: |
Fri, 28 Feb 2020 16:38:11 +0000 |
From: Sai Pavan Boddu <address@hidden>
The GICv2 allows the implementation to implement a variable number
of priority bits; unimplemented bits in the priority registers
are read as zeros, writes ignored. We were previously always
implementing a full 8 bits of priority, which is allowed but not
what the real hardware typically does (which is usually to have
4 or 5 bits of priority).
Add a new device property to allow the number of implemented
property bits to be specified.
Signed-off-by: Sai Pavan Boddu <address@hidden>
Message-id: address@hidden
Suggested-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: improved commit message]
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/intc/arm_gic.h | 2 ++
include/hw/intc/arm_gic_common.h | 1 +
hw/intc/arm_gic.c | 33 ++++++++++++++++++++++++++++++--
hw/intc/arm_gic_common.c | 1 +
4 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index ed703a17203..303b9748cbb 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -68,6 +68,8 @@
/* Number of SGI target-list bits */
#define GIC_TARGETLIST_BITS 8
+#define GIC_MAX_PRIORITY_BITS 8
+#define GIC_MIN_PRIORITY_BITS 4
#define TYPE_ARM_GIC "arm_gic"
#define ARM_GIC(obj) \
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index b5585fec451..6e0d6b8a889 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -96,6 +96,7 @@ typedef struct GICState {
uint16_t priority_mask[GIC_NCPU_VCPU];
uint16_t running_priority[GIC_NCPU_VCPU];
uint16_t current_pending[GIC_NCPU_VCPU];
+ uint32_t n_prio_bits;
/* If we present the GICv2 without security extensions to a guest,
* the guest can configure the GICC_CTLR to configure group 1 binary point
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1d7da7baa20..c60dc6b5e6e 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -641,6 +641,23 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu,
MemTxAttrs attrs)
return ret;
}
+static uint32_t gic_fullprio_mask(GICState *s, int cpu)
+{
+ /*
+ * Return a mask word which clears the unimplemented priority
+ * bits from a priority value for an interrupt. (Not to be
+ * confused with the group priority, whose mask depends on BPR.)
+ */
+ int priBits;
+
+ if (gic_is_vcpu(cpu)) {
+ priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS;
+ } else {
+ priBits = s->n_prio_bits;
+ }
+ return ~0U << (8 - priBits);
+}
+
void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
MemTxAttrs attrs)
{
@@ -651,6 +668,8 @@ void gic_dist_set_priority(GICState *s, int cpu, int irq,
uint8_t val,
val = 0x80 | (val >> 1); /* Non-secure view */
}
+ val &= gic_fullprio_mask(s, cpu);
+
if (irq < GIC_INTERNAL) {
s->priority1[irq][cpu] = val;
} else {
@@ -669,7 +688,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu,
int irq,
}
prio = (prio << 1) & 0xff; /* Non-secure view */
}
- return prio;
+ return prio & gic_fullprio_mask(s, cpu);
}
static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
@@ -684,7 +703,7 @@ static void gic_set_priority_mask(GICState *s, int cpu,
uint8_t pmask,
return;
}
}
- s->priority_mask[cpu] = pmask;
+ s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu);
}
static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)
@@ -2055,6 +2074,16 @@ static void arm_gic_realize(DeviceState *dev, Error
**errp)
return;
}
+ if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS ||
+ (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS :
+ s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) {
+ error_setg(errp, "num-priority-bits cannot be greater than %d"
+ " or less than %d", GIC_MAX_PRIORITY_BITS,
+ s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS :
+ GIC_MIN_PRIORITY_BITS);
+ return;
+ }
+
/* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
* enabled, virtualization extensions related interfaces (main virtual
* interface (s->vifaceiomem[0]) and virtual CPU interface).
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index e6c4fe7a5a4..7b44d5625b6 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] = {
DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
/* True if the GIC should implement the virtualization extensions */
DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
+ DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),
DEFINE_PROP_END_OF_LIST(),
};
--
2.20.1
- [PULL 00/33] target-arm queue, Peter Maydell, 2020/02/28
- [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port, Peter Maydell, 2020/02/28
- [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn, Peter Maydell, 2020/02/28
- [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller, Peter Maydell, 2020/02/28
- [PULL 04/33] arm_gic: Mask the un-supported priority bits,
Peter Maydell <=
- [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2, Peter Maydell, 2020/02/28
- [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4, Peter Maydell, 2020/02/28
- [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd, Peter Maydell, 2020/02/28
- [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}, Peter Maydell, 2020/02/28
- [PULL 11/33] target/arm: Perform fpdp_v2 check first, Peter Maydell, 2020/02/28
- [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Peter Maydell, 2020/02/28
- [PULL 13/33] target/arm: Add missing checks for fpsp_v2, Peter Maydell, 2020/02/28
- [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac, Peter Maydell, 2020/02/28
- [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn, Peter Maydell, 2020/02/28
- [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode, Peter Maydell, 2020/02/28