Re: [PULL v2 00/46] target-arm queue

[Peter Maydell]

On Fri, 21 Feb 2020 at 16:18, Peter Maydell <address@hidden> wrote:
>
> v1->v2 changes: dropped the last 6 patches from rth as there's
> a problem with one of them that's too complicated to try to
> fix up.
>
> thanks
> -- PMM
>
> The following changes since commit a8c6af67e1e8d460e2c6e87070807e0a02c0fec2:
>
>   Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200221' 
> into staging (2020-02-21 14:20:42 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20200221-1
>
> for you to fetch changes up to 9eb4f58918a851fb46895fd9b7ce579afeac9d02:
>
>   target/arm: Set MVFR0.FPSP for ARMv5 cpus (2020-02-21 16:07:03 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * aspeed/scu: Implement chip ID register
>  * hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
>  * mainstone: Make providing flash images non-mandatory
>  * z2: Make providing flash images non-mandatory
>  * Fix failures to flush SVE high bits after AdvSIMD 
> INS/ZIP/UZP/TRN/TBL/TBX/EXT
>  * Minor performance improvement: spend less time recalculating hflags values
>  * Code cleanup to isar_feature function tests
>  * Implement ARMv8.1-PMU and ARMv8.4-PMU extensions
>  * Bugfix: correct handling of PMCR_EL0.LC bit
>  * Bugfix: correct definition of PMCRDP
>  * Correctly implement ACTLR2, HACTLR2
>  * allwinner: Wire up USB ports
>  * Vectorize emulation of USHL, SSHL, PMUL*
>  * xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
>  * sh4: Fix PCI ISA IO memory subregion
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM