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[PULL 34/52] target/arm: Correctly implement ACTLR2, HACTLR2
From: |
Peter Maydell |
Subject: |
[PULL 34/52] target/arm: Correctly implement ACTLR2, HACTLR2 |
Date: |
Fri, 21 Feb 2020 13:07:22 +0000 |
The ACTLR2 and HACTLR2 AArch32 system registers didn't exist in ARMv7
or the original ARMv8. They were later added as optional registers,
whose presence is signaled by the ID_MMFR4.AC2 field. From ARMv8.2
they are mandatory (ie ID_MMFR4.AC2 must be non-zero).
We implemented HACTLR2 in commit 0e0456ab8895a5e85, but we
incorrectly made it exist for all v8 CPUs, and we didn't implement
ACTLR2 at all.
Sort this out by implementing both registers only when they are
supposed to exist, and setting the ID_MMFR4 bit for -cpu max.
Note that this removes HACTLR2 from our Cortex-A53, -A47 and -A72
CPU models; this is correct, because those CPUs do not implement
this register.
Fixes: 0e0456ab8895a5e85
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 5 +++++
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 4 ++++
target/arm/helper.c | 32 +++++++++++++++++++++++---------
4 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c6af3290caf..b4c83a1cb52 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3531,6 +3531,11 @@ static inline bool isar_feature_aa32_hpd(const
ARMISARegisters *id)
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
}
+static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
+}
+
/*
* 64-bit feature tests via id registers.
*/
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c46bb5a5c09..9f618e120aa 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2718,6 +2718,7 @@ static void arm_max_initfn(Object *obj)
t = cpu->isar.id_mmfr4;
t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
cpu->isar.id_mmfr4 = t;
}
#endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 8430d432943..0929401a4dd 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -703,6 +703,10 @@ static void aarch64_max_initfn(Object *obj)
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->isar.id_mmfr3 = u;
+ u = cpu->isar.id_mmfr4;
+ u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+ cpu->isar.id_mmfr4 = u;
+
u = cpu->isar.id_aa64dfr0;
u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
cpu->isar.id_aa64dfr0 = u;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 19d749a1913..1ac09f387ed 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6862,6 +6862,27 @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
};
#endif
+/*
+ * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
+ * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
+ * is non-zero, which is never for ARMv7, optionally in ARMv8
+ * and mandatorily for ARMv8.2 and up.
+ * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
+ * implementation is RAZ/WI we can ignore this detail, as we
+ * do for ACTLR.
+ */
+static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
+ { .name = "ACTLR2", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+ { .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
+ .access = PL2_RW, .type = ARM_CP_CONST,
+ .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@@ -7623,15 +7644,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, auxcr_reginfo);
- if (arm_feature(env, ARM_FEATURE_V8)) {
- /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
- ARMCPRegInfo hactlr2_reginfo = {
- .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
- .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
- .access = PL2_RW, .type = ARM_CP_CONST,
- .resetvalue = 0
- };
- define_one_arm_cp_reg(cpu, &hactlr2_reginfo);
+ if (cpu_isar_feature(aa32_ac2, cpu)) {
+ define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo);
}
}
--
2.20.1
- [PULL 24/52] target/arm: Move DBGDIDR into ARMISARegisters, (continued)
- [PULL 24/52] target/arm: Move DBGDIDR into ARMISARegisters, Peter Maydell, 2020/02/21
- [PULL 26/52] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/21
- [PULL 25/52] target/arm: Read debug-related ID registers from KVM, Peter Maydell, 2020/02/21
- [PULL 27/52] target/arm: Implement ARMv8.4-PMU extension, Peter Maydell, 2020/02/21
- [PULL 29/52] target/arm: Correct definition of PMCRDP, Peter Maydell, 2020/02/21
- [PULL 28/52] target/arm: Provide ARMv8.4-PMU in '-cpu max', Peter Maydell, 2020/02/21
- [PULL 30/52] target/arm: Correct handling of PMCR_EL0.LC bit, Peter Maydell, 2020/02/21
- [PULL 32/52] target/arm: Use isar_feature function for testing AA32HPD feature, Peter Maydell, 2020/02/21
- [PULL 33/52] target/arm: Use FIELD_EX32 for testing 32-bit fields, Peter Maydell, 2020/02/21
- [PULL 31/52] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks, Peter Maydell, 2020/02/21
- [PULL 34/52] target/arm: Correctly implement ACTLR2, HACTLR2,
Peter Maydell <=
- [PULL 35/52] hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file, Peter Maydell, 2020/02/21
- [PULL 37/52] arm: allwinner: Wire up USB ports, Peter Maydell, 2020/02/21
- [PULL 36/52] hcd-ehci: Introduce "companion-enable" sysbus property, Peter Maydell, 2020/02/21
- [PULL 39/52] target/arm: Convert PMUL.8 to gvec, Peter Maydell, 2020/02/21
- [PULL 42/52] xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd, Peter Maydell, 2020/02/21
- [PULL 40/52] target/arm: Convert PMULL.64 to gvec, Peter Maydell, 2020/02/21
- [PULL 38/52] target/arm: Vectorize USHL and SSHL, Peter Maydell, 2020/02/21
- [PULL 41/52] target/arm: Convert PMULL.8 to gvec, Peter Maydell, 2020/02/21
- [PULL 44/52] target/arm: Rename isar_feature_aa32_simd_r32, Peter Maydell, 2020/02/21
- [PULL 45/52] target/arm: Use isar_feature_aa32_simd_r32 more places, Peter Maydell, 2020/02/21