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Re: [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2]
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2] |
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Date: |
Fri, 14 Feb 2020 18:35:59 +0000 |
On Fri, 14 Feb 2020 at 18:15, Richard Henderson
<address@hidden> wrote:
>
> These registers are 32-bits wide. Cut and paste used FIELD_EX64
> instead of the more proper FIELD_EX32. In practice all this did
> was use an unnecessary 64-bit operation, producing correct results.
>
> Signed-off-by: Richard Henderson <address@hidden>
This is a duplicate with:
https://patchew.org/QEMU/address@hidden/address@hidden/
which I got out the door very slightly before your series
hit my mailbox :-)
-- PMM
- [PATCH 00/19] target/arm: vfp feature and decodetree cleanup, Richard Henderson, 2020/02/14
- [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2], Richard Henderson, 2020/02/14
- [PATCH 03/19] target/arm: Use isar_feature_aa32_simd_r32 more places, Richard Henderson, 2020/02/14
- [PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32, Richard Henderson, 2020/02/14
- [PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2, Richard Henderson, 2020/02/14
- [PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus, Richard Henderson, 2020/02/14
- [PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}, Richard Henderson, 2020/02/14