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[PULL 10/46] target/arm: Add arm_mmu_idx_is_stage1_of_2
From: |
Peter Maydell |
Subject: |
[PULL 10/46] target/arm: Add arm_mmu_idx_is_stage1_of_2 |
Date: |
Thu, 13 Feb 2020 14:41:09 +0000 |
From: Richard Henderson <address@hidden>
Use a common predicate for querying stage1-ness.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/internals.h | 18 ++++++++++++++++++
target/arm/helper.c | 8 +++-----
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 6d4a942bde4..1f8ee5f573e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1034,6 +1034,24 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState
*env)
ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
#endif
+/**
+ * arm_mmu_idx_is_stage1_of_2:
+ * @mmu_idx: The ARMMMUIdx to test
+ *
+ * Return true if @mmu_idx is a NOTLB mmu_idx that is the
+ * first stage of a two stage regime.
+ */
+static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
+{
+ switch (mmu_idx) {
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
+ return true;
+ default:
+ return false;
+ }
+}
+
/*
* Parameters of a given virtual address, as extracted from the
* translation control register (TCR) for a given regime.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7d15d5c933c..57dc7a307c0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3261,8 +3261,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
bool take_exc = false;
if (fi.s1ptw && current_el == 1 && !arm_is_secure(env)
- && (mmu_idx == ARMMMUIdx_Stage1_E1 ||
- mmu_idx == ARMMMUIdx_Stage1_E0)) {
+ && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
/*
* Synchronous stage 2 fault on an access made as part of the
* translation table walk for AT S1E0* or AT S1E1* insn
@@ -9285,8 +9284,7 @@ static inline bool
regime_translation_disabled(CPUARMState *env,
}
}
- if ((env->cp15.hcr_el2 & HCR_DC) &&
- (mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1)) {
+ if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
/* HCR.DC means SCTLR_EL1.M behaves as 0 */
return true;
}
@@ -9595,7 +9593,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
hwaddr addr, MemTxAttrs txattrs,
ARMMMUFaultInfo *fi)
{
- if ((mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1) &&
+ if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
!regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
target_ulong s2size;
hwaddr s2pa;
--
2.20.1
- [PULL 01/46] i.MX: Fix inverted register bits in wdt code., (continued)
- [PULL 01/46] i.MX: Fix inverted register bits in wdt code., Peter Maydell, 2020/02/13
- [PULL 04/46] arm/virt/acpi: remove meaningless sub device "RP0" from PCI0, Peter Maydell, 2020/02/13
- [PULL 03/46] bios-tables-test: prepare to change ARM virt ACPI DSDT, Peter Maydell, 2020/02/13
- [PULL 02/46] i.MX: Add support for WDT on i.MX6, Peter Maydell, 2020/02/13
- [PULL 06/46] arm/acpi: fix PCI _PRT definition, Peter Maydell, 2020/02/13
- [PULL 05/46] arm/virt/acpi: remove _ADR from devices identified by _HID, Peter Maydell, 2020/02/13
- [PULL 07/46] arm/acpi: fix duplicated _UID of PCI interrupt link devices, Peter Maydell, 2020/02/13
- [PULL 08/46] arm/acpi: simplify the description of PCI _CRS, Peter Maydell, 2020/02/13
- [PULL 09/46] virt/acpi: update golden masters for DSDT update, Peter Maydell, 2020/02/13
- [PULL 12/46] target/arm: Add isar_feature tests for PAN + ATS1E1, Peter Maydell, 2020/02/13
- [PULL 10/46] target/arm: Add arm_mmu_idx_is_stage1_of_2,
Peter Maydell <=
- [PULL 14/46] target/arm: Split out aarch32_cpsr_valid_mask, Peter Maydell, 2020/02/13
- [PULL 15/46] target/arm: Mask CPSR_J when Jazelle is not enabled, Peter Maydell, 2020/02/13
- [PULL 11/46] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled, Peter Maydell, 2020/02/13
- [PULL 19/46] target/arm: Introduce aarch64_pstate_valid_mask, Peter Maydell, 2020/02/13
- [PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask, Peter Maydell, 2020/02/13
- [PULL 22/46] target/arm: Enforce PAN semantics in get_S1prot, Peter Maydell, 2020/02/13
- [PULL 17/46] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return, Peter Maydell, 2020/02/13
- [PULL 18/46] target/arm: Remove CPSR_RESERVED, Peter Maydell, 2020/02/13
- [PULL 21/46] target/arm: Update arm_mmu_idx_el for PAN, Peter Maydell, 2020/02/13
- [PULL 20/46] target/arm: Update MSR access for PAN, Peter Maydell, 2020/02/13