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[PATCH v4 08/20] target/arm: Use aarch32_cpsr_valid_mask in helper_excep
From: |
Richard Henderson |
Subject: |
[PATCH v4 08/20] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return |
Date: |
Sat, 8 Feb 2020 12:58:04 +0000 |
Using ~0 as the mask on the aarch64->aarch32 exception return
was not even as correct as the CPSR_ERET_MASK that we had used
on the aarch32->aarch32 exception return.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper-a64.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index bf45f8a785..0c9feba392 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -959,7 +959,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t
new_pc)
{
int cur_el = arm_current_el(env);
unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
- uint32_t spsr = env->banked_spsr[spsr_idx];
+ uint32_t mask, spsr = env->banked_spsr[spsr_idx];
int new_el;
bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
@@ -1014,7 +1014,8 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t
new_pc)
* will sort the register banks out for us, and we've already
* caught all the bad-mode cases in el_from_spsr().
*/
- cpsr_write(env, spsr, ~0, CPSRWriteRaw);
+ mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
+ cpsr_write(env, spsr, mask, CPSRWriteRaw);
if (!arm_singlestep_active(env)) {
env->uncached_cpsr &= ~PSTATE_SS;
}
--
2.20.1
- [PATCH v4 03/20] target/arm: Add isar_feature tests for PAN + ATS1E1, (continued)
- [PATCH v4 03/20] target/arm: Add isar_feature tests for PAN + ATS1E1, Richard Henderson, 2020/02/08
- [PATCH v4 04/20] target/arm: Move LOR regdefs to file scope, Richard Henderson, 2020/02/08
- [PATCH v4 02/20] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled, Richard Henderson, 2020/02/08
- [PATCH v4 05/20] target/arm: Split out aarch32_cpsr_valid_mask, Richard Henderson, 2020/02/08
- [PATCH v4 06/20] target/arm: Mask CPSR_J when Jazelle is not enabled, Richard Henderson, 2020/02/08
- [PATCH v4 08/20] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return,
Richard Henderson <=
- [PATCH v4 07/20] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask, Richard Henderson, 2020/02/08
- [PATCH v4 09/20] target/arm: Remove CPSR_RESERVED, Richard Henderson, 2020/02/08
- [PATCH v4 10/20] target/arm: Introduce aarch64_pstate_valid_mask, Richard Henderson, 2020/02/08
- [PATCH v4 11/20] target/arm: Update MSR access for PAN, Richard Henderson, 2020/02/08
- [PATCH v4 12/20] target/arm: Update arm_mmu_idx_el for PAN, Richard Henderson, 2020/02/08
- [PATCH v4 13/20] target/arm: Enforce PAN semantics in get_S1prot, Richard Henderson, 2020/02/08
- [PATCH v4 14/20] target/arm: Set PAN bit as required on exception entry, Richard Henderson, 2020/02/08
- [PATCH v4 15/20] target/arm: Implement ATS1E1 system registers, Richard Henderson, 2020/02/08