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[PULL 32/48] target/arm: Flush tlbs for E2&0 translation regime
From: |
Peter Maydell |
Subject: |
[PULL 32/48] target/arm: Flush tlbs for E2&0 translation regime |
Date: |
Fri, 7 Feb 2020 14:33:27 +0000 |
From: Richard Henderson <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 25 ++++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f9be6b052f0..3b7b459314d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4174,8 +4174,12 @@ static CPAccessResult aa64_cacheop_access(CPUARMState
*env,
static int vae1_tlbmask(CPUARMState *env)
{
+ /* Since we exclude secure first, we may read HCR_EL2 directly. */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
+ } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
+ == (HCR_E2H | HCR_TGE)) {
+ return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0;
} else {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
@@ -4219,6 +4223,12 @@ static int alle1_tlbmask(CPUARMState *env)
}
}
+static int e2_tlbmask(CPUARMState *env)
+{
+ /* TODO: ARMv8.4-SecEL2 */
+ return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2;
+}
+
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4231,10 +4241,10 @@ static void tlbi_aa64_alle1_write(CPUARMState *env,
const ARMCPRegInfo *ri,
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = e2_tlbmask(env);
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx(cs, mask);
}
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4259,8 +4269,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
+ int mask = e2_tlbmask(env);
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4278,11 +4289,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env,
const ARMCPRegInfo *ri,
* Currently handles both VAE2 and VALE2, since we don't support
* flush-last-level-only.
*/
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = e2_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.20.1
- [PULL 20/48] target/arm: Reorganize ARMMMUIdx, (continued)
- [PULL 20/48] target/arm: Reorganize ARMMMUIdx, Peter Maydell, 2020/02/07
- [PULL 23/48] target/arm: Update arm_sctlr for VHE, Peter Maydell, 2020/02/07
- [PULL 24/48] target/arm: Update aa64_zva_access for EL2, Peter Maydell, 2020/02/07
- [PULL 25/48] target/arm: Update ctr_el0_access for EL2, Peter Maydell, 2020/02/07
- [PULL 26/48] target/arm: Add the hypervisor virtual counter, Peter Maydell, 2020/02/07
- [PULL 27/48] target/arm: Update timer access for VHE, Peter Maydell, 2020/02/07
- [PULL 28/48] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Peter Maydell, 2020/02/07
- [PULL 31/48] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Peter Maydell, 2020/02/07
- [PULL 29/48] target/arm: Add VHE system register redirection and aliasing, Peter Maydell, 2020/02/07
- [PULL 30/48] target/arm: Add VHE timer register redirection and aliasing, Peter Maydell, 2020/02/07
- [PULL 32/48] target/arm: Flush tlbs for E2&0 translation regime,
Peter Maydell <=
- [PULL 33/48] target/arm: Update arm_phys_excp_target_el for TGE, Peter Maydell, 2020/02/07
- [PULL 34/48] target/arm: Update {fp,sve}_exception_el for VHE, Peter Maydell, 2020/02/07
- [PULL 35/48] target/arm: check TGE and E2H flags for EL0 pauth traps, Peter Maydell, 2020/02/07
- [PULL 36/48] target/arm: Update get_a64_user_mem_index for VHE, Peter Maydell, 2020/02/07
- [PULL 38/48] target/arm: Enable ARMv8.1-VHE in -cpu max, Peter Maydell, 2020/02/07
- [PULL 37/48] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE, Peter Maydell, 2020/02/07
- [PULL 40/48] target/arm: Pass more cpu state to arm_excp_unmasked, Peter Maydell, 2020/02/07
- [PULL 41/48] target/arm: Use bool for unmasked in arm_excp_unmasked, Peter Maydell, 2020/02/07
- [PULL 43/48] bcm2835_dma: Fix the ylen loop in TD mode, Peter Maydell, 2020/02/07
- [PULL 39/48] target/arm: Move arm_excp_unmasked to cpu.c, Peter Maydell, 2020/02/07