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[PULL 22/48] target/arm: Update arm_mmu_idx for VHE
From: |
Peter Maydell |
Subject: |
[PULL 22/48] target/arm: Update arm_mmu_idx for VHE |
Date: |
Fri, 7 Feb 2020 14:33:17 +0000 |
From: Richard Henderson <address@hidden>
Return the indexes for the EL2&0 regime when the appropriate bits
are set within HCR_EL2.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f7bc7f1a8de..9f8d7ca1f36 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11318,12 +11318,16 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
}
+ /* See ARM pseudo-function ELIsInHost. */
switch (el) {
case 0:
- /* TODO: ARMv8.1-VHE */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdx_SE10_0;
}
+ if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)
+ && arm_el_is_aa64(env, 2)) {
+ return ARMMMUIdx_E20_0;
+ }
return ARMMMUIdx_E10_0;
case 1:
if (arm_is_secure_below_el3(env)) {
@@ -11331,8 +11335,11 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
}
return ARMMMUIdx_E10_1;
case 2:
- /* TODO: ARMv8.1-VHE */
/* TODO: ARMv8.4-SecEL2 */
+ /* Note that TGE does not apply at EL2. */
+ if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) {
+ return ARMMMUIdx_E20_2;
+ }
return ARMMMUIdx_E2;
case 3:
return ARMMMUIdx_SE3;
--
2.20.1
- [PULL 11/48] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, (continued)
- [PULL 11/48] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Peter Maydell, 2020/02/07
- [PULL 12/48] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Peter Maydell, 2020/02/07
- [PULL 13/48] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01], Peter Maydell, 2020/02/07
- [PULL 14/48] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Peter Maydell, 2020/02/07
- [PULL 17/48] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, Peter Maydell, 2020/02/07
- [PULL 19/48] target/arm: Tidy ARMMMUIdx m-profile definitions, Peter Maydell, 2020/02/07
- [PULL 18/48] target/arm: Rearrange ARMMMUIdxBit, Peter Maydell, 2020/02/07
- [PULL 16/48] target/arm: Recover 4 bits from TBFLAGs, Peter Maydell, 2020/02/07
- [PULL 15/48] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Peter Maydell, 2020/02/07
- [PULL 21/48] target/arm: Add regime_has_2_ranges, Peter Maydell, 2020/02/07
- [PULL 22/48] target/arm: Update arm_mmu_idx for VHE,
Peter Maydell <=
- [PULL 20/48] target/arm: Reorganize ARMMMUIdx, Peter Maydell, 2020/02/07
- [PULL 23/48] target/arm: Update arm_sctlr for VHE, Peter Maydell, 2020/02/07
- [PULL 24/48] target/arm: Update aa64_zva_access for EL2, Peter Maydell, 2020/02/07
- [PULL 25/48] target/arm: Update ctr_el0_access for EL2, Peter Maydell, 2020/02/07
- [PULL 26/48] target/arm: Add the hypervisor virtual counter, Peter Maydell, 2020/02/07
- [PULL 27/48] target/arm: Update timer access for VHE, Peter Maydell, 2020/02/07
- [PULL 28/48] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Peter Maydell, 2020/02/07
- [PULL 31/48] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Peter Maydell, 2020/02/07
- [PULL 29/48] target/arm: Add VHE system register redirection and aliasing, Peter Maydell, 2020/02/07
- [PULL 30/48] target/arm: Add VHE timer register redirection and aliasing, Peter Maydell, 2020/02/07