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[PATCH v7 39/41] target/arm: Pass more cpu state to arm_excp_unmasked
From: |
Richard Henderson |
Subject: |
[PATCH v7 39/41] target/arm: Pass more cpu state to arm_excp_unmasked |
Date: |
Thu, 6 Feb 2020 10:54:46 +0000 |
Avoid redundant computation of cpu state by passing it in
from the caller, which has already computed it for itself.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b81ed44bd2..fcee0a2dd4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s)
}
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
- unsigned int target_el)
+ unsigned int target_el,
+ unsigned int cur_el, bool secure,
+ uint64_t hcr_el2)
{
CPUARMState *env = cs->env_ptr;
- unsigned int cur_el = arm_current_el(env);
- bool secure = arm_is_secure(env);
bool pstate_unmasked;
int8_t unmasked = 0;
- uint64_t hcr_el2;
/*
* Don't take exceptions if they target a lower EL.
@@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned
int excp_idx,
return false;
}
- hcr_el2 = arm_hcr_el2_eff(env);
-
switch (excp_idx) {
case EXCP_FIQ:
pstate_unmasked = !(env->daif & PSTATE_F);
@@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
CPUARMState *env = cs->env_ptr;
uint32_t cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
uint32_t target_el;
uint32_t excp_idx;
bool ret = false;
@@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
if (interrupt_request & CPU_INTERRUPT_FIQ) {
excp_idx = EXCP_FIQ;
target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
cc->do_interrupt(cs);
@@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD) {
excp_idx = EXCP_IRQ;
target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
cc->do_interrupt(cs);
@@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
if (interrupt_request & CPU_INTERRUPT_VIRQ) {
excp_idx = EXCP_VIRQ;
target_el = 1;
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
cc->do_interrupt(cs);
@@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
if (interrupt_request & CPU_INTERRUPT_VFIQ) {
excp_idx = EXCP_VFIQ;
target_el = 1;
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
cc->do_interrupt(cs);
--
2.20.1
- [PATCH v7 24/41] target/arm: Update ctr_el0_access for EL2, (continued)
- [PATCH v7 24/41] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2020/02/06
- [PATCH v7 19/41] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2020/02/06
- [PATCH v7 23/41] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2020/02/06
- [PATCH v7 32/41] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2020/02/06
- [PATCH v7 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/02/06
- [PATCH v7 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/02/06
- [PATCH v7 28/41] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2020/02/06
- [PATCH v7 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2020/02/06
- [PATCH v7 39/41] target/arm: Pass more cpu state to arm_excp_unmasked,
Richard Henderson <=
- [PATCH v7 33/41] target/arm: Update {fp,sve}_exception_el for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 38/41] target/arm: Move arm_excp_unmasked to cpu.c, Richard Henderson, 2020/02/06
- [PATCH v7 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt, Richard Henderson, 2020/02/06
- [PATCH v7 22/41] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 21/41] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 31/41] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2020/02/06
- [PATCH v7 29/41] target/arm: Add VHE timer register redirection and aliasing, Richard Henderson, 2020/02/06
- [PATCH v7 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2020/02/06
- [PATCH v7 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 35/41] target/arm: Update get_a64_user_mem_index for VHE, Richard Henderson, 2020/02/06