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[PATCH v3 09/20] target/arm: Tidy msr_mask
From: |
Richard Henderson |
Subject: |
[PATCH v3 09/20] target/arm: Tidy msr_mask |
Date: |
Mon, 3 Feb 2020 14:47:05 +0000 |
The CPSR_USER mask for IS_USER already avoids all of the RES0
bits as per aarch32_cpsr_valid_mask. Fix up the formatting.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 42 ++++++++++++++++++++++++------------------
1 file changed, 24 insertions(+), 18 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 032f7074cb..2b3bfcf7ca 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2734,28 +2734,34 @@ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1,
int x, int y)
/* Return the mask of PSR bits set by a MSR instruction. */
static uint32_t msr_mask(DisasContext *s, int flags, int spsr)
{
- uint32_t mask;
+ uint32_t mask = 0;
- mask = 0;
- if (flags & (1 << 0))
+ if (flags & (1 << 0)) {
mask |= 0xff;
- if (flags & (1 << 1))
- mask |= 0xff00;
- if (flags & (1 << 2))
- mask |= 0xff0000;
- if (flags & (1 << 3))
- mask |= 0xff000000;
-
- /* Mask out undefined bits. */
- mask &= aarch32_cpsr_valid_mask(s->features, s->isar);
-
- /* Mask out execution state and reserved bits. */
- if (!spsr) {
- mask &= ~CPSR_EXEC;
}
- /* Mask out privileged bits. */
- if (IS_USER(s))
+ if (flags & (1 << 1)) {
+ mask |= 0xff00;
+ }
+ if (flags & (1 << 2)) {
+ mask |= 0xff0000;
+ }
+ if (flags & (1 << 3)) {
+ mask |= 0xff000000;
+ }
+
+ if (IS_USER(s)) {
+ /* Mask out privileged bits. */
mask &= CPSR_USER;
+ } else {
+ /* Mask out undefined bits. */
+ mask &= aarch32_cpsr_valid_mask(s->features, s->isar);
+
+ /* Mask out execution state and reserved bits. */
+ if (!spsr) {
+ mask &= ~CPSR_EXEC;
+ }
+ }
+
return mask;
}
--
2.20.1
- [PATCH v3 03/20] target/arm: Add isar_feature tests for PAN + ATS1E1, (continued)
- [PATCH v3 03/20] target/arm: Add isar_feature tests for PAN + ATS1E1, Richard Henderson, 2020/02/03
- [PATCH v3 04/20] target/arm: Move LOR regdefs to file scope, Richard Henderson, 2020/02/03
- [PATCH v3 02/20] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled, Richard Henderson, 2020/02/03
- [PATCH v3 05/20] target/arm: Split out aarch32_cpsr_valid_mask, Richard Henderson, 2020/02/03
- [PATCH v3 07/20] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return, Richard Henderson, 2020/02/03
- [PATCH v3 08/20] target/arm: Remove CPSR_RESERVED, Richard Henderson, 2020/02/03
- [PATCH v3 09/20] target/arm: Tidy msr_mask,
Richard Henderson <=
- [PATCH v3 06/20] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask, Richard Henderson, 2020/02/03
- [PATCH v3 10/20] target/arm: Introduce aarch64_pstate_valid_mask, Richard Henderson, 2020/02/03
- [PATCH v3 11/20] target/arm: Update MSR access for PAN, Richard Henderson, 2020/02/03
- [PATCH v3 12/20] target/arm: Update arm_mmu_idx_el for PAN, Richard Henderson, 2020/02/03
- [PATCH v3 13/20] target/arm: Enforce PAN semantics in get_S1prot, Richard Henderson, 2020/02/03