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[PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro
From: |
Alistair Francis |
Subject: |
[PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro |
Date: |
Fri, 31 Jan 2020 17:03:08 -0800 |
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_bits.h | 11 +++++++++++
target/riscv/cpu_helper.c | 4 ++--
target/riscv/op_helper.c | 2 +-
target/riscv/translate.c | 2 +-
4 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 049032f2ae..7f64ee1174 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -363,8 +363,19 @@
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
+#if defined(TARGET_RISCV64)
#define MSTATUS_MTL 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
+#elif defined(TARGET_RISCV32)
+#define MSTATUS_MTL 0x00000040
+#define MSTATUS_MPV 0x00000080
+#endif
+
+#ifdef TARGET_RISCV32
+# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV)
+#else
+# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV)
+#endif
#define MSTATUS64_UXL 0x0000000300000000ULL
#define MSTATUS64_SXL 0x0000000C00000000ULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e04545adf7..b9e90dfd9a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -322,7 +322,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
mode = get_field(env->mstatus, MSTATUS_MPP);
if (riscv_has_ext(env, RVH) &&
- get_field(env->mstatus, MSTATUS_MPV)) {
+ MSTATUS_MPV_ISSET(env)) {
use_background = true;
}
}
@@ -720,7 +720,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
m_mode_two_stage = env->priv == PRV_M &&
access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV) &&
- get_field(env->mstatus, MSTATUS_MPV);
+ MSTATUS_MPV_ISSET(env);
hs_mode_two_stage = env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index dca68fa96e..8736f689c2 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -146,7 +146,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
cpu_pc_deb)
target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
- target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV);
+ target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 240fd7c971..ae8818efb3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -752,7 +752,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->virt_enabled = riscv_cpu_virt_enabled(env);
if (env->priv_ver == PRV_M &&
get_field(env->mstatus, MSTATUS_MPRV) &&
- get_field(env->mstatus, MSTATUS_MPV)) {
+ MSTATUS_MPV_ISSET(env)) {
ctx->virt_enabled = true;
} else if (env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
--
2.25.0
- [PATCH v2 24/35] target/riscv: Remove the hret instruction, (continued)
- [PATCH v2 24/35] target/riscv: Remove the hret instruction, Alistair Francis, 2020/01/31
- [PATCH v2 23/35] target/riscv: Add hfence instructions, Alistair Francis, 2020/01/31
- [PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2020/01/31
- [PATCH v2 28/35] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2020/01/31
- [PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty, Alistair Francis, 2020/01/31
- [PATCH v2 29/35] target/riscv: Allow specifying MMU stage, Alistair Francis, 2020/01/31
- [PATCH v2 32/35] target/riscv: Set htval and mtval2 on execptions, Alistair Francis, 2020/01/31
- [PATCH v2 30/35] target/riscv: Implement second stage MMU, Alistair Francis, 2020/01/31
- [PATCH v2 31/35] target/riscv: Raise the new execptions when 2nd stage translation fails, Alistair Francis, 2020/01/31
- [PATCH v2 33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2020/01/31
- [PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro,
Alistair Francis <=
- [PATCH v2 35/35] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2020/01/31