[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses
From: |
Alistair Francis |
Subject: |
[PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses |
Date: |
Fri, 31 Jan 2020 17:02:07 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/csr.c | 116 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index bee639e92e..3fa8d2cfda 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -273,6 +273,7 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE
| SSTATUS_SPIE |
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP |
MIP_VSEIP;
+static const target_ulong vsip_writable_mask = MIP_VSSIP;
#if defined(TARGET_RISCV32)
static const char valid_vm_1_09[16] = {
@@ -878,6 +879,111 @@ static int write_hgatp(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+/* Virtual CSR Registers */
+static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vsstatus;
+ return 0;
+}
+
+static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->vsstatus = val;
+ return 0;
+}
+
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ int ret = rmw_mip(env, 0, ret_value, new_value,
+ write_mask & env->mideleg & vsip_writable_mask);
+ return ret;
+}
+
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
+ return 0;
+}
+
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
+{
+ target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg &
MIP_VSSIP);
+ return write_mie(env, CSR_MIE, newval);
+}
+
+static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vstvec;
+ return 0;
+}
+
+static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->vstvec = val;
+ return 0;
+}
+
+static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vsscratch;
+ return 0;
+}
+
+static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->vsscratch = val;
+ return 0;
+}
+
+static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vsepc;
+ return 0;
+}
+
+static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->vsepc = val;
+ return 0;
+}
+
+static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vscause;
+ return 0;
+}
+
+static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->vscause = val;
+ return 0;
+}
+
+static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vstval;
+ return 0;
+}
+
+static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->vstval = val;
+ return 0;
+}
+
+static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->vsatp;
+ return 0;
+}
+
+static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->vsatp = val;
+ return 0;
+}
+
/* Physical Memory Protection */
static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -1091,6 +1197,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HTINST] = { hmode, read_htinst, write_htinst
},
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp
},
+ [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus
},
+ [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip
},
+ [CSR_VSIE] = { hmode, read_vsie, write_vsie
},
+ [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec
},
+ [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch
},
+ [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc
},
+ [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause
},
+ [CSR_VSTVAL] = { hmode, read_vstval, write_vstval
},
+ [CSR_VSATP] = { hmode, read_vsatp, write_vsatp
},
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
--
2.25.0
- [PATCH v2 02/35] target/riscv: Add the Hypervisor extension, (continued)
- [PATCH v2 02/35] target/riscv: Add the Hypervisor extension, Alistair Francis, 2020/01/31
- [PATCH v2 03/35] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2020/01/31
- [PATCH v2 04/35] target/riscv: Add support for the new execption numbers, Alistair Francis, 2020/01/31
- [PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs, Alistair Francis, 2020/01/31
- [PATCH v2 06/35] target/riscv: Add the virtulisation mode, Alistair Francis, 2020/01/31
- [PATCH v2 07/35] target/riscv: Add the force HS exception mode, Alistair Francis, 2020/01/31
- [PATCH v2 08/35] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2020/01/31
- [PATCH v2 09/35] target/riscv: Print priv and virt in disas log, Alistair Francis, 2020/01/31
- [PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2020/01/31
- [PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2020/01/31
- [PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses,
Alistair Francis <=
- [PATCH v2 13/35] target/riscv: Add Hypervisor machine CSRs accesses, Alistair Francis, 2020/01/31
- [PATCH v2 14/35] target/riscv: Add virtual register swapping function, Alistair Francis, 2020/01/31
- [PATCH v2 17/35] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2020/01/31
- [PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2020/01/31
- [PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2020/01/31
- [PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2020/01/31
- [PATCH v2 21/35] target/riscv: Add hypvervisor trap support, Alistair Francis, 2020/01/31
- [PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2020/01/31
- [PATCH v2 19/35] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2020/01/31
- [PATCH v2 22/35] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2020/01/31