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Re: [PATCH 10/11] target/arm: Implement ATS1E1 system registers
From: |
Richard Henderson |
Subject: |
Re: [PATCH 10/11] target/arm: Implement ATS1E1 system registers |
Date: |
Fri, 31 Jan 2020 13:38:06 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 12/9/19 5:41 AM, Peter Maydell wrote:
>> case 1:
>> - mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
>> + if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
>> + mmu_idx = secure ? ARMMMUIdx_SE1_PAN :
>> ARMMMUIdx_Stage1_E1_PAN;
>> + } else {
>> + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
>> + }
>
> This way of writing it is fine, but just to check my understanding:
> if the CPSR_PAN bit isn't set, then will a lookup via Idx_SE1_PAN
> and a lookup via Idx_SE1 return the same results?
No.
> Or do we guarantee that we only use the _PAN versions of the indexes
> if the PAN bit is actually active?
Yes. We enforce the PAN behaviour based on *_PAN deep within a
get_phys_addr_lpae subroutine. See patch 8.
r~
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