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Re: [PATCH v5 28/41] target/arm: Add VHE system register redirection and
From: |
Peter Maydell |
Subject: |
Re: [PATCH v5 28/41] target/arm: Add VHE system register redirection and aliasing |
Date: |
Fri, 31 Jan 2020 13:31:58 +0000 |
On Wed, 29 Jan 2020 at 23:56, Richard Henderson
<address@hidden> wrote:
>
> Several of the EL1/0 registers are redirected to the EL2 version when in
> EL2 and HCR_EL2.E2H is set. Many of these registers have side effects.
> Link together the two ARMCPRegInfo structures after they have been
> properly instantiated. Install common dispatch routines to all of the
> relevant registers.
>
> The same set of registers that are redirected also have additional
> EL12/EL02 aliases created to access the original register that was
> redirected.
>
> Omit the generic timer registers from redirection here, because we'll
> need multiple kinds of redirection from both EL0 and EL2.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> v5: Drop unioning in ARMCPRegInfo with bank_fieldoffsets[].
> ---
> + for (i = 0; i < ARRAY_SIZE(aliases); i++) {
> + const struct E2HAlias *a = &aliases[i];
> + ARMCPRegInfo *src_reg, *dst_reg;
> +
> + if (a->feature && !a->feature(&cpu->isar)) {
> + continue;
> + }
> +
> + src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
> + dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
> + g_assert(src_reg != NULL);
> + g_assert(dst_reg != NULL);
> +
> + /* Cross-compare names to detect typos in the keys. */
> + g_assert(strcmp(src_reg->name, a->src_name) == 0);
> + g_assert(strcmp(dst_reg->name, a->dst_name) == 0);
> +
> + /* None of the core system registers use opaque; we will. */
> + g_assert(src_reg->opaque == NULL);
> +
> + /* Create alias before redirection so we dup the right data. */
> + if (a->new_key) {
> + ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
> + uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
> + bool ok;
> +
> + new_reg->name = a->new_name;
> + new_reg->type |= ARM_CP_ALIAS;
> + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
> + new_reg->access &= 0xf0;
That seems like it would be more clear written as
new_reg->access &= (PL2_RW | PL3_RW);
(strictly there the PL3_RW is useless as PL2_RW implies it but
it captures the intent better I think)
> +
> + ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
> + g_assert(ok);
> + }
> +
> + src_reg->opaque = dst_reg;
> + src_reg->orig_readfn = src_reg->readfn ?: raw_read;
> + src_reg->orig_writefn = src_reg->writefn ?: raw_write;
> + if (!src_reg->raw_readfn) {
> + src_reg->raw_readfn = raw_read;
> + }
> + if (!src_reg->raw_writefn) {
> + src_reg->raw_writefn = raw_write;
> + }
> + src_reg->readfn = el2_e2h_read;
> + src_reg->writefn = el2_e2h_write;
> + }
> +}
> +#endif
Otherwise
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [PATCH v5 22/41] target/arm: Update arm_sctlr for VHE, (continued)
- [PATCH v5 22/41] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/01/29
- [PATCH v5 24/41] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2020/01/29
- [PATCH v5 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/01/29
- [PATCH v5 31/41] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2020/01/29
- [PATCH v5 28/41] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2020/01/29
- Re: [PATCH v5 28/41] target/arm: Add VHE system register redirection and aliasing,
Peter Maydell <=
- [PATCH v5 29/41] target/arm: Add VHE timer register redirection and aliasing, Richard Henderson, 2020/01/29
- [PATCH v5 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2020/01/29
- [PATCH v5 32/41] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2020/01/29
- [PATCH v5 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2020/01/29
- [PATCH v5 33/41] target/arm: Update {fp,sve}_exception_el for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 39/41] target/arm: Pass more cpu state to arm_excp_unmasked, Richard Henderson, 2020/01/29
- [PATCH v5 38/41] target/arm: Move arm_excp_unmasked to cpu.c, Richard Henderson, 2020/01/29
- [PATCH v5 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked, Richard Henderson, 2020/01/29
- [PATCH v5 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt, Richard Henderson, 2020/01/29