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[PULL 11/34] ppc/pnv: remove useless "core-pir" property alias.
From: |
David Gibson |
Subject: |
[PULL 11/34] ppc/pnv: remove useless "core-pir" property alias. |
Date: |
Fri, 31 Jan 2020 17:09:01 +1100 |
From: Cédric Le Goater <address@hidden>
Commit 158e17a65e1a ("ppc/pnv: Link "chip" property to PnvCore::chip
pointer") introduced some cleanups of the PnvCore realize handler.
Let's continue by reworking a bit the interface of the PnvCore
handlers for the CPU threads. These changes make the "core-pir"
property alias unused. Remove it.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv_core.c | 28 +++++++++++++---------------
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 8ca5fbd1a9..5fe3f21e12 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -40,11 +40,11 @@ static const char *pnv_core_cpu_typename(PnvCore *pc)
return cpu_type;
}
-static void pnv_core_cpu_reset(PowerPCCPU *cpu, PnvChip *chip)
+static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
cpu_reset(cs);
@@ -56,7 +56,7 @@ static void pnv_core_cpu_reset(PowerPCCPU *cpu, PnvChip *chip)
env->nip = 0x10;
env->msr |= MSR_HVB; /* Hypervisor mode */
- pcc->intc_reset(chip, cpu);
+ pcc->intc_reset(pc->chip, cpu);
}
/*
@@ -162,14 +162,14 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_cpu_realize(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
+static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
{
CPUPPCState *env = &cpu->env;
int core_pir;
int thread_index = 0; /* TODO: TCG supports only one thread */
ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
Error *local_err = NULL;
- PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
if (local_err) {
@@ -177,13 +177,13 @@ static void pnv_core_cpu_realize(PowerPCCPU *cpu, PnvChip
*chip, Error **errp)
return;
}
- pcc->intc_create(chip, cpu, &local_err);
+ pcc->intc_create(pc->chip, cpu, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
+ core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
/*
* The PIR of a thread is the core PIR + the thread index. We will
@@ -203,7 +203,7 @@ static void pnv_core_reset(void *dev)
int i;
for (i = 0; i < cc->nr_threads; i++) {
- pnv_core_cpu_reset(pc->threads[i], pc->chip);
+ pnv_core_cpu_reset(pc, pc->threads[i]);
}
}
@@ -231,8 +231,6 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
snprintf(name, sizeof(name), "thread[%d]", i);
object_property_add_child(OBJECT(pc), name, obj, &error_abort);
- object_property_add_alias(obj, "core-pir", OBJECT(pc),
- "pir", &error_abort);
cpu->machine_data = g_new0(PnvCPUState, 1);
@@ -240,7 +238,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
}
for (j = 0; j < cc->nr_threads; j++) {
- pnv_core_cpu_realize(pc->threads[j], pc->chip, &local_err);
+ pnv_core_cpu_realize(pc, pc->threads[j], &local_err);
if (local_err) {
goto err;
}
@@ -263,12 +261,12 @@ err:
error_propagate(errp, local_err);
}
-static void pnv_core_cpu_unrealize(PowerPCCPU *cpu, PnvChip *chip)
+static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu)
{
PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
- PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
- pcc->intc_destroy(chip, cpu);
+ pcc->intc_destroy(pc->chip, cpu);
cpu_remove_sync(CPU(cpu));
cpu->machine_data = NULL;
g_free(pnv_cpu);
@@ -284,7 +282,7 @@ static void pnv_core_unrealize(DeviceState *dev, Error
**errp)
qemu_unregister_reset(pnv_core_reset, pc);
for (i = 0; i < cc->nr_threads; i++) {
- pnv_core_cpu_unrealize(pc->threads[i], pc->chip);
+ pnv_core_cpu_unrealize(pc, pc->threads[i]);
}
g_free(pc->threads);
}
--
2.24.1
- [PULL 00/34] ppc-for-5.0 queue 20200131, David Gibson, 2020/01/31
- [PULL 03/34] ppc:virtex_ml507: remove unused arguments, David Gibson, 2020/01/31
- [PULL 02/34] ppc/pnv: improve error logging when a PNOR update fails, David Gibson, 2020/01/31
- [PULL 10/34] ppc/pnv: Add support for HRMOR on Radix host, David Gibson, 2020/01/31
- [PULL 01/34] ppc/pnv: use QEMU unit definition MiB, David Gibson, 2020/01/31
- [PULL 05/34] target/ppc: Clarify the meaning of return values in kvm_handle_debug, David Gibson, 2020/01/31
- [PULL 06/34] spapr: Fail CAS if option vector table cannot be parsed, David Gibson, 2020/01/31
- [PULL 11/34] ppc/pnv: remove useless "core-pir" property alias.,
David Gibson <=
- [PULL 12/34] ppc/pnv: Add support for "hostboot" mode, David Gibson, 2020/01/31
- [PULL 16/34] tpm_spapr: Support suspend and resume, David Gibson, 2020/01/31
- [PULL 09/34] spapr: Don't allow multiple active vCPUs at CAS, David Gibson, 2020/01/31
- [PULL 08/34] target/ppc: add support for Hypervisor Facility Unavailable Exception, David Gibson, 2020/01/31
- [PULL 13/34] tpm: Move tpm_tis_show_buffer to tpm_util.c, David Gibson, 2020/01/31
- [PULL 15/34] tpm_spapr: Support TPM for ppc64 using CRQ based interface, David Gibson, 2020/01/31
- [PULL 07/34] target/ppc: Add privileged message send facilities, David Gibson, 2020/01/31
- [PULL 22/34] spapr: Enable DD2.3 accelerated count cache flush in pseries-5.0 machine, David Gibson, 2020/01/31
- [PULL 24/34] Wrapper function to wait on condition for the main loop mutex, David Gibson, 2020/01/31
- [PULL 21/34] ppc/pnv: change the PowerNV machine devices to be non user creatable, David Gibson, 2020/01/31