[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC v3 21/25] intel_iommu: do not pass down pasid bind for PASID #0
From: |
Liu, Yi L |
Subject: |
[RFC v3 21/25] intel_iommu: do not pass down pasid bind for PASID #0 |
Date: |
Wed, 29 Jan 2020 04:16:52 -0800 |
From: Liu Yi L <address@hidden>
RID_PASID field was introduced in VT-d 3.0 spec, it is used
for DMA requests w/o PASID in scalable mode VT-d. It is also
known as IOVA. And in VT-d 3.1 spec, there is definition on it:
"Implementations not supporting RID_PASID capability
(ECAP_REG.RPS is 0b), use a PASID value of 0 to perform
address translation for requests without PASID."
This patch adds a check against the PASIDs which are going to be
bound to device. For PASID #0, it is not necessary to pass down
pasid bind request for it since PASID #0 is used as RID_PASID for
DMA requests without pasid. Further reason is current Intel vIOMMU
supports gIOVA by shadowing guest 2nd level page table. However,
in future, if guest IOMMU driver uses 1st level page table to store
IOVA mappings, then guest IOVA support will also be done via nested
translation. When gIOVA is over FLPT, then vIOMMU should pass down
the pasid bind request for PASID #0 to host, host needs to bind the
guest IOVA page table to a proper PASID. e.g PASID value in RID_PASID
field for PF/VF if ECAP_REG.RPS is clear or default PASID for ADI
(Assignable Device Interface in Scalable IOV solution).
IOVA over FLPT support on Intel VT-d:
https://lkml.org/lkml/2019/9/23/297
Cc: Kevin Tian <address@hidden>
Cc: Jacob Pan <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: Yi Sun <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Signed-off-by: Liu Yi L <address@hidden>
---
hw/i386/intel_iommu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 6422add..a511289 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1883,6 +1883,16 @@ static int vtd_bind_guest_pasid(IntelIOMMUState *s,
VTDBus *vtd_bus,
struct iommu_gpasid_bind_data *g_bind_data;
int ret = -1;
+ if (pasid < VTD_MIN_HPASID) {
+ /*
+ * If pasid < VTD_HPASID_MIN, this pasid is not allocated
+ * from host. No need to pass down the changes on it to host.
+ * TODO: when IOVA over FLPT is ready, this switch should be
+ * refined.
+ */
+ return 0;
+ }
+
vtd_icx = vtd_bus->dev_icx[devfn];
if (!vtd_icx) {
return ret;
--
2.7.4
- [RFC v3 13/25] intel_iommu: modify x-scalable-mode to be string option, (continued)
- [RFC v3 13/25] intel_iommu: modify x-scalable-mode to be string option, Liu, Yi L, 2020/01/29
- [RFC v3 11/25] vfio: get stage-1 pasid formats from Kernel, Liu, Yi L, 2020/01/29
- [RFC v3 15/25] intel_iommu: process pasid cache invalidation, Liu, Yi L, 2020/01/29
- [RFC v3 14/25] intel_iommu: add virtual command capability support, Liu, Yi L, 2020/01/29
- [RFC v3 16/25] intel_iommu: add PASID cache management infrastructure, Liu, Yi L, 2020/01/29
- [RFC v3 17/25] vfio: add bind stage-1 page table support, Liu, Yi L, 2020/01/29
- [RFC v3 18/25] intel_iommu: bind/unbind guest page table to host, Liu, Yi L, 2020/01/29
- [RFC v3 19/25] intel_iommu: replay guest pasid bindings to host, Liu, Yi L, 2020/01/29
- [RFC v3 20/25] intel_iommu: replay pasid binds after context cache invalidation, Liu, Yi L, 2020/01/29
- [RFC v3 22/25] vfio: add support for flush iommu stage-1 cache, Liu, Yi L, 2020/01/29
- [RFC v3 21/25] intel_iommu: do not pass down pasid bind for PASID #0,
Liu, Yi L <=
- [RFC v3 23/25] intel_iommu: process PASID-based iotlb invalidation, Liu, Yi L, 2020/01/29
- [RFC v3 24/25] intel_iommu: propagate PASID-based iotlb invalidation to host, Liu, Yi L, 2020/01/29
- [RFC v3 25/25] intel_iommu: process PASID-based Device-TLB invalidation, Liu, Yi L, 2020/01/29
- Re: [RFC v3 00/25] intel_iommu: expose Shared Virtual Addressing to VMs, no-reply, 2020/01/29
- Re: [RFC v3 00/25] intel_iommu: expose Shared Virtual Addressing to VMs, no-reply, 2020/01/29