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Re: [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastr
From: |
Aleksandar Markovic |
Subject: |
Re: [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit instructions |
Date: |
Sat, 25 Jan 2020 00:38:47 +0100 |
On Friday, January 24, 2020, Richard Henderson <address@hidden> wrote:
On 1/24/20 10:56 AM, Aleksandar Markovic wrote:
>
>
> On Friday, January 24, 2020, Richard Henderson <address@hidden
> <mailto:address@hidden>> wrote:
>
> On 1/24/20 6:38 AM, Aleksandar Markovic wrote:
> > The basic disassembly logic was obtained by somewhat modified script
> > decodetree.py, and such output was further manually modified to
> > handle numerous details of micromips 32R6 instruction coding scheme.
>
> What modifications to the script?
> What manual modifications to the output?
>
> It's been a while since I looked at micromips, but I don't recall anything so
> odd that it couldn't be handled with the current output of decodetree.py.
>
>
> I don't have dev setup at hand right now, but I can look it up in few days.
> Some of the changes are purely of cosmetic nature (like outputing binary
> instead of hex codes), but some are not. I can send you the whole modified
> script, once I come back to my desk. There are some not-so-obvious micromips
> oddities, if one delves enough into the coding scheme.
The thing I'm concerned about here is any future maintenance of this file. One
would surely prefer to edit the original decodetree input than this output.
Here is the deal: This dissasembler is meant to reflect the documentation of a particular ISA, and as the documentation largely stays constant (except adding some insignificant errata), the disassembler will stay virtually constant, we wouldn't like even to touch it, and we like it this way.
r~
- [PATCH v4 3/7] target/mips: Amend CP0 WatchHi register implementation, (continued)
- [PATCH v4 3/7] target/mips: Amend CP0 WatchHi register implementation, Aleksandar Markovic, 2020/01/24
- [PATCH v4 1/7] target/mips: Rectify documentation on deprecating r4k machine, Aleksandar Markovic, 2020/01/24
- [PATCH v4 2/7] target/mips: Add support for MIPS<32|64>R6 CRC32 ISA, Aleksandar Markovic, 2020/01/24
- [PATCH v4 4/7] target/mips: Add implementation of GINVT instruction, Aleksandar Markovic, 2020/01/24
- [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit instructions, Aleksandar Markovic, 2020/01/24
- Re: [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit instructions, Richard Henderson, 2020/01/24
- Re: [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit instructions, Aleksandar Markovic, 2020/01/24
- Re: [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit instructions, Richard Henderson, 2020/01/24
- Re: [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit instructions,
Aleksandar Markovic <=
- Re: [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit instructions, Richard Henderson, 2020/01/25
- Re: [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit instructions, Aleksandar Markovic, 2020/01/25
- Re: [PATCH v4 6/7] disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit instructions, Richard Henderson, 2020/01/25
[PATCH v4 7/7] disas: mips: Add micromips R6 disassembler - 32-bit instructions, Aleksandar Markovic, 2020/01/24
Re: [PATCH v4 0/7] target/mips: Misc MIPS fixes and improvements for 5.0, no-reply, 2020/01/24
Re: [PATCH v4 0/7] target/mips: Misc MIPS fixes and improvements for 5.0, no-reply, 2020/01/24