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Re: [PATCH 0/2] RISC-V TIME CSR for privileged mode

From: Jonathan Behrens
Subject: Re: [PATCH 0/2] RISC-V TIME CSR for privileged mode
Date: Tue, 21 Jan 2020 08:11:05 -0500

This series doesn't seem to touch mcounteren.TM which should be hardwired to zero if no callback in provided, and writable otherwise. (I had a patch to do the hardwiring unconditionally, but it seems to have been accidentally dropped.) Other than that, I think the design is quite good.


On Tue, Jan 21, 2020 at 3:59 AM Anup Patel <address@hidden> wrote:
This series adds emulation of TIME CSRs for privileged mode. With
this series, we see approximately 25+% improvement in hackbench
numbers for non-virtualized (or Host) Linux and 40+% improvement
in hackbench numbers for Guest/VM Linux.

These patches are based on mainline/alistair/riscv-hyp-ext-v0.5.1
branch of https://github.com/kvm-riscv/qemu.git and can be found
in riscv_time_csr_v1 branch of same repo.

Anup Patel (2):
  target/riscv: Emulate TIME CSRs for privileged mode
  hw/riscv: Provide rdtime callback for TCG in CLINT emulation

 hw/riscv/sifive_clint.c   |  1 +
 target/riscv/cpu.h        |  5 +++
 target/riscv/cpu_helper.c |  5 +++
 target/riscv/csr.c        | 80 +++++++++++++++++++++++++++++++++++++--
 4 files changed, 87 insertions(+), 4 deletions(-)


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