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Re: [PATCH] docs: qemu-cpu-models: Document '-noTSX' variants and 'mds-n
Re: [PATCH] docs: qemu-cpu-models: Document '-noTSX' variants and 'mds-no'
Fri, 17 Jan 2020 14:22:58 +0100
On Thu, Jan 16, 2020 at 06:36:38PM +0100, Kashyap Chamarthy wrote:
> (2) There are _three_ variants[+] of CascadeLake CPUs, with different
> stepping levels: 5, 6, and 7. To quite wikichip.org[*]:
> "note that while steppings 6 & 7 are fully mitigated, earlier
> stepping 5 is not protected against MSBDS, MLPDS, nor MDSUM"
> The above is also indicated in the Intel's manual itself[+], as
> indicated by "No" under the three columns of MFBDS, MSBDS, and
> Signed-off-by: Kashyap Chamarthy <address@hidden>
> - I think I also need to add a note about 'tsx-ctrl' bit. Here too,
> same question as above -- does it show up in /proc/cpuinfo/?
While at it ... if I mention 'mds-no', then it would be inconsistent,
and inaccurate, if I don't also mention 'taa-no' IA32_ARCH_CAPABILITIES
In short, I should mention the following MSR bits, and their use, in
... while bearing in mind that none (?) of these MSR bits will show up
under /proc/cpuinfo in the guest, rather they're used to populate the
relevant vulnerability file in sysfs