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[PULL 23/38] target/i386: Add missed features to Cooperlake CPU model
From: |
Paolo Bonzini |
Subject: |
[PULL 23/38] target/i386: Add missed features to Cooperlake CPU model |
Date: |
Wed, 8 Jan 2020 13:32:40 +0100 |
From: Xiaoyao Li <address@hidden>
It lacks VMX features and two security feature bits (disclosed recently) in
MSR_IA32_ARCH_CAPABILITIES in current Cooperlake CPU model, so add them.
Fixes: 22a866b6166d ("i386: Add new CPU model Cooperlake")
Signed-off-by: Xiaoyao Li <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
target/i386/cpu.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 31556b7..41f28ce 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3198,7 +3198,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
.features[FEAT_ARCH_CAPABILITIES] =
MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
- MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO,
+ MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
+ MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
.features[FEAT_7_1_EAX] =
CPUID_7_1_EAX_AVX512_BF16,
/*
@@ -3213,6 +3214,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
+ /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC
scaling */
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
+ MSR_VMX_BASIC_TRUE_CTLS,
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
VMX_VM_ENTRY_LOAD_IA32_PAT |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB
|
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT |
MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS |
MSR_VMX_EPT_AD_BITS,
+ .features[FEAT_VMX_EXIT_CTLS] =
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
+ .features[FEAT_VMX_PROCBASED_CTLS] =
VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS
|
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+ .features[FEAT_VMX_SECONDARY_CTLS] =
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT
|
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+ VMX_SECONDARY_EXEC_ENABLE_VPID |
VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING |
VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS
|
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Cooperlake)",
},
--
1.8.3.1
- [PULL 13/38] hw/ppc/Kconfig: Let the Sam460ex board use the PowerPC 405 devices, (continued)
- [PULL 13/38] hw/ppc/Kconfig: Let the Sam460ex board use the PowerPC 405 devices, Paolo Bonzini, 2020/01/08
- [PULL 14/38] hw/ppc/Kconfig: Let the Xilinx Virtex5 ML507 use the PPC-440 devices, Paolo Bonzini, 2020/01/08
- [PULL 15/38] hw/ppc/Makefile: Simplify the sPAPR PCI objects rule, Paolo Bonzini, 2020/01/08
- [PULL 16/38] hw/ppc/Kconfig: Only select fw_cfg with machines using OpenBIOS, Paolo Bonzini, 2020/01/08
- [PULL 17/38] hw/ppc/Kconfig: Only select FDT helper for machines using it, Paolo Bonzini, 2020/01/08
- [PULL 19/38] hw/nvram/Kconfig: Restrict CHRP NVRAM to machines using OpenBIOS or SLOF, Paolo Bonzini, 2020/01/08
- [PULL 18/38] hw/nvram/Kconfig: Add an entry for the NMC93xx EEPROM, Paolo Bonzini, 2020/01/08
- [PULL 20/38] hw/rtc/mc146818: Add missing dependency on ISA Bus, Paolo Bonzini, 2020/01/08
- [PULL 21/38] target/i386: Fix handling of k_gs_base register in 32-bit mode in gdbstub, Paolo Bonzini, 2020/01/08
- [PULL 22/38] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES, Paolo Bonzini, 2020/01/08
- [PULL 23/38] target/i386: Add missed features to Cooperlake CPU model,
Paolo Bonzini <=
- [PULL 25/38] hw/ipmi: Explicit we ignore some QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 24/38] hw/ipmi: Remove unnecessary declarations, Paolo Bonzini, 2020/01/08
- [PULL 26/38] hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 27/38] hw/usb/dev-serial: Explicit we ignore few QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 28/38] hw/usb/redirect: Explicit we ignore few QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 29/38] ccid-card-passthru: Explicit we ignore QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 30/38] vhost-user-crypto: Explicit we ignore some QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 31/38] vhost-user-net: Explicit we ignore few QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 32/38] vhost-user-blk: Explicit we ignore few QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08
- [PULL 34/38] monitor/qmp: Explicit we ignore few QEMUChrEvent in IOEventHandler, Paolo Bonzini, 2020/01/08