Re: [PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses

[Palmer Dabbelt]

On Mon, 09 Dec 2019 10:11:17 PST (-0800), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <address@hidden>
> ---
>  target/riscv/csr.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index aaca1a6a0f..74e911af08 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -985,6 +985,30 @@ static int write_vsatp(CPURISCVState *env, int csrno, 
> target_ulong val)
>      return 0;
>  }
>
> +static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> +    *val = env->mtval2;
> +    return 0;
> +}
> +
> +static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
> +{
> +    env->mtval2 = val;
> +    return 0;
> +}
> +
> +static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> +    *val = env->mtinst;
> +    return 0;
> +}
> +
> +static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
> +{
> +    env->mtinst = val;
> +    return 0;
> +}
> +
>  /* Physical Memory Protection */
>  static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
>  {
> @@ -1208,6 +1232,9 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>      [CSR_VSTVAL] =              { hmode,   read_vstval,      write_vstval     
> },
>      [CSR_VSATP] =               { hmode,   read_vsatp,       write_vsatp      
> },
>
> +    [CSR_MTVAL2] =              { hmode,   read_mtval2,      write_mtval2     
> },
> +    [CSR_MTINST] =              { hmode,   read_mtinst,      write_mtinst     
> },
> +
>      /* Physical Memory Protection */
>      [CSR_PMPCFG0  ... CSR_PMPADDR9] =  { pmp,   read_pmpcfg,  write_pmpcfg   },
>      [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp,   read_pmpaddr, write_pmpaddr  },

Reviewed-by: Palmer Dabbelt <address@hidden>