Re: QEMU for Qualcomm Hexagon - KVM Forum talk and code available

[Philippe Mathieu-Daudé]

On 12/17/19 7:21 PM, Peter Maydell wrote:
> On Tue, 17 Dec 2019 at 18:16, Taylor Simpson <address@hidden> wrote:
> > Question 1:
> > I see this error from checkpatch.pl
> > ERROR: Macros with complex values should be enclosed in parenthesis
> > However, there are times when the code will not compile with parenthesis.  For 
> > example, we have a file that defined all the instruction attributes.  Each line 
> > has
> > DEF_ATTRIB(LOAD, "Loads from memory", "", "")
> > So, we create an enum of all the possible attributes as follows
> > enum {
> > #define DEF_ATTRIB(NAME, ...) A_##NAME,
> > #include "attribs_def.h"
> > #undef DEF_ATTRIB
> > };
>
> checkpatch is often right, but also often wrong,
> especially for C macros which are in the general case
> impossible to parse. If the error makes no sense, you can
> ignore it.
>
> > Question 2:
> > What is the best source of guidance on breaking down support for a new target 
> > into a patch series?
>
> Look at how previous ports did it.

Recent ports were system (softmmu), this is a linux-user port. The last 
architecture merged is RISCV, they did that with commit, so I'm not sure 
this is our best example on breaking down:

$ git show --stat ea10325917c8
commit ea10325917c8a8f92611025c85950c00f826cb73
Author: Michael Clark <address@hidden>
Date:   Sat Mar 3 01:31:10 2018 +1300

    RISC-V Disassembler

    The RISC-V disassembler has no dependencies outside of the 'disas'
    directory so it can be applied independently. The majority of the
    disassembler is machine-generated from instruction set metadata:

    - https://github.com/michaeljclark/riscv-meta

    Expected checkpatch errors for consistency and brevity reasons:

    ERROR: line over 90 characters
    ERROR: trailing statements should be on next line
    ERROR: space prohibited between function name and open parenthesis '('

    Reviewed-by: Richard Henderson <address@hidden>
    Signed-off-by: Michael Clark <address@hidden>

 include/disas/bfd.h |    2 +
 disas.c             |    2 +
 disas/riscv.c       | 3048 
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 disas/Makefile.objs |    1 +
 4 files changed, 3053 insertions(+)

$ git show --stat 55c2a12cbcd3d
commit 55c2a12cbcd3d417de39ee82dfe1d26b22a07116
Author: Michael Clark <address@hidden>
Date:   Sat Mar 3 01:31:11 2018 +1300

    RISC-V TCG Code Generation

    TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
    RISC-V code generator has complete coverage for the Base ISA v2.2,
    Privileged ISA v1.9.1 and Privileged ISA v1.10:

    - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
    - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
    - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10

    Reviewed-by: Richard Henderson <address@hidden>
    Signed-off-by: Bastian Koppelmann <address@hidden>
    Signed-off-by: Sagar Karandikar <address@hidden>
    Signed-off-by: Michael Clark <address@hidden>

 target/riscv/instmap.h   |  364 ++++++++++++++++++++++++++++++++++++++
 target/riscv/translate.c | 1978 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 2342 insertions(+)

$ git show --stat 47ae93cdfed
commit 47ae93cdfedc683c56e19113d516d7ce4971c8e6
Author: Michael Clark <address@hidden>
Date:   Sat Mar 3 01:31:11 2018 +1300

    RISC-V Linux User Emulation

    Implementation of linux user emulation for RISC-V.

    Reviewed-by: Richard Henderson <address@hidden>
    Signed-off-by: Sagar Karandikar <address@hidden>
    Signed-off-by: Michael Clark <address@hidden>

 linux-user/riscv/syscall_nr.h     | 287 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 linux-user/riscv/target_cpu.h     |  18 +++++++++++++
 linux-user/riscv/target_elf.h     |  14 ++++++++++
 linux-user/riscv/target_signal.h  |  23 ++++++++++++++++
 linux-user/riscv/target_structs.h |  46 ++++++++++++++++++++++++++++++++
 linux-user/riscv/target_syscall.h |  56 
++++++++++++++++++++++++++++++++++++++
 linux-user/riscv/termbits.h       | 222 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 linux-user/syscall_defs.h         |  13 +++++----
 target/riscv/cpu_user.h           |  13 +++++++++
 linux-user/elfload.c              |  22 +++++++++++++++
 linux-user/main.c                 |  99 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 linux-user/signal.c               | 203 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 linux-user/syscall.c              |   2 ++
 13 files changed, 1012 insertions(+), 6 deletions(-)


> Also I thought we'd
> had a subthread on how best to split things up, but maybe I'm
> misremembering.

I remember something too, I hope you are right :P

> >   I see avr being reviewed currently.  I have mostly new files: 12 in 
> > linux-user/hexagon, and ~50 in target/hexagon.  I also need to add test cases 
> > and a container for the toolchain.  Is it OK to break things down mostly at 
> > file boundaries?
>
> No, file boundaries are generally a bad choice of breakdown.
> You want to split at conceptual boundaries, ie one chunk
> of functionality that can be comprehended in one go without
> having to refer forward to other patches.
>
> thanks
> -- PMM