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[PULL 74/88] ppc/pnv: Fix OCC common area region mapping
From: |
David Gibson |
Subject: |
[PULL 74/88] ppc/pnv: Fix OCC common area region mapping |
Date: |
Tue, 17 Dec 2019 15:43:08 +1100 |
From: Cédric Le Goater <address@hidden>
The OCC common area is mapped at a unique address on the system and
each OCC is assigned a segment to expose its sensor data :
-------------------------------------------------------------------------
| Start (Offset from | End | Size |Description |
| BAR2 base address) | | | |
-------------------------------------------------------------------------
| 0x00580000 | 0x005A57FF |150kB |OCC 0 Sensor Data Block|
| 0x005A5800 | 0x005CAFFF |150kB |OCC 1 Sensor Data Block|
| : | : | : | : |
| 0x00686800 | 0x006ABFFF |150kB |OCC 7 Sensor Data Block|
| 0x006AC000 | 0x006FFFFF |336kB |Reserved |
-------------------------------------------------------------------------
Maximum size is 1.5MB.
We could define a "OCC common area" memory region at the machine level
and sub regions for each OCC. But it adds some extra complexity to the
models. Fix the current layout with a simpler model.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 4 ++--
hw/ppc/pnv_occ.c | 11 ++++-------
include/hw/ppc/pnv.h | 4 ++++
include/hw/ppc/pnv_occ.h | 8 ++++++--
4 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index af7317a86d..0be0b6b411 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1065,7 +1065,7 @@ static void pnv_chip_power8_realize(DeviceState *dev,
Error **errp)
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA_BASE,
+ memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
&chip8->occ.sram_regs);
/* HOMER */
@@ -1278,7 +1278,7 @@ static void pnv_chip_power9_realize(DeviceState *dev,
Error **errp)
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
/* OCC SRAM model */
- memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA_BASE,
+ memory_region_add_subregion(get_system_memory(),
PNV9_OCC_SENSOR_BASE(chip),
&chip9->occ.sram_regs);
/* HOMER */
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 765c0a6ce5..924fdabc9e 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -167,9 +167,7 @@ static void pnv_occ_power8_class_init(ObjectClass *klass,
void *data)
PnvOCCClass *poc = PNV_OCC_CLASS(klass);
poc->xscom_size = PNV_XSCOM_OCC_SIZE;
- poc->sram_size = PNV_OCC_COMMON_AREA_SIZE;
poc->xscom_ops = &pnv_occ_power8_xscom_ops;
- poc->sram_ops = &pnv_occ_sram_ops;
poc->psi_irq = PSIHB_IRQ_OCC;
}
@@ -240,9 +238,7 @@ static void pnv_occ_power9_class_init(ObjectClass *klass,
void *data)
PnvOCCClass *poc = PNV_OCC_CLASS(klass);
poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
- poc->sram_size = PNV9_OCC_COMMON_AREA_SIZE;
poc->xscom_ops = &pnv_occ_power9_xscom_ops;
- poc->sram_ops = &pnv_occ_sram_ops;
poc->psi_irq = PSIHB9_IRQ_OCC;
}
@@ -266,9 +262,10 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
occ, "xscom-occ", poc->xscom_size);
- /* XScom region for OCC SRAM registers */
- pnv_xscom_region_init(&occ->sram_regs, OBJECT(dev), poc->sram_ops,
- occ, "occ-common-area", poc->sram_size);
+ /* OCC common area mmio region for OCC SRAM registers */
+ memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
+ occ, "occ-common-area",
+ PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
}
static Property pnv_occ_properties[] = {
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 301c7e62fa..92f80b1cce 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -246,6 +246,8 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
+#define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
+ PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
#define PNV_HOMER_SIZE 0x0000000000400000ull
#define PNV_HOMER_BASE(chip) \
@@ -312,6 +314,8 @@ IPMIBmc *pnv_bmc_create(void);
#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
+#define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
+ PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
#define PNV9_HOMER_SIZE 0x0000000000400000ull
#define PNV9_HOMER_BASE(chip) \
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index 66b0989be6..f8d3061419 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -29,6 +29,9 @@
#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
#define PNV9_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV9_OCC)
+#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
+#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
+
typedef struct PnvOCC {
DeviceState xd;
@@ -50,10 +53,11 @@ typedef struct PnvOCCClass {
DeviceClass parent_class;
int xscom_size;
- int sram_size;
const MemoryRegionOps *xscom_ops;
- const MemoryRegionOps *sram_ops;
int psi_irq;
} PnvOCCClass;
+#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
+ (PNV_OCC_SENSOR_DATA_BLOCK_OFFSET + (i) * PNV_OCC_SENSOR_DATA_BLOCK_SIZE)
+
#endif /* PPC_PNV_OCC_H */
--
2.23.0
- [PULL 63/88] ppc/psi: cleanup definitions, (continued)
- [PULL 63/88] ppc/psi: cleanup definitions, David Gibson, 2019/12/16
- [PULL 70/88] ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes, David Gibson, 2019/12/16
- [PULL 68/88] target/ppc: Add SPR ASDR, David Gibson, 2019/12/16
- [PULL 62/88] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine, David Gibson, 2019/12/16
- [PULL 59/88] ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM, David Gibson, 2019/12/16
- [PULL 75/88] ppc: Drop useless extern annotation for functions, David Gibson, 2019/12/16
- [PULL 66/88] target/ppc: Implement the VTB for HV access, David Gibson, 2019/12/16
- [PULL 71/88] ppc/pnv: populate the DT with realized XSCOM devices, David Gibson, 2019/12/16
- [PULL 67/88] target/ppc: Work [S]PURR implementation and add HV support, David Gibson, 2019/12/16
- [PULL 83/88] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom(), David Gibson, 2019/12/16
- [PULL 74/88] ppc/pnv: Fix OCC common area region mapping,
David Gibson <=
- [PULL 81/88] ppc/pnv: Introduce PnvChipClass::intc_print_info() method, David Gibson, 2019/12/16
- [PULL 72/88] ppc/pnv: Make PnvXScomInterface an incomplete type, David Gibson, 2019/12/16
- [PULL 80/88] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers, David Gibson, 2019/12/16
- [PULL 76/88] ppc/pnv: Introduce PnvPsiClass::compat, David Gibson, 2019/12/16
- [PULL 84/88] ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom(), David Gibson, 2019/12/16
- [PULL 77/88] ppc/pnv: Drop PnvPsiClass::chip_type, David Gibson, 2019/12/16
- [PULL 82/88] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method, David Gibson, 2019/12/16
- [PULL 78/88] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat, David Gibson, 2019/12/16
- [PULL 79/88] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt(), David Gibson, 2019/12/16
- [PULL 73/88] ppc/pnv: Introduce PBA registers, David Gibson, 2019/12/16