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[PULL 33/88] ppc/pnv: Fix TIMA indirect access
From: |
David Gibson |
Subject: |
[PULL 33/88] ppc/pnv: Fix TIMA indirect access |
Date: |
Tue, 17 Dec 2019 15:42:27 +1100 |
From: Cédric Le Goater <address@hidden>
When the TIMA of a CPU needs to be accessed from the indirect page,
the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0
register. This thread id is relative to the chip and not to the system.
Introduce a helper routine to look for a CPU of a given PIR and fix
pnv_xive_get_indirect_tctx() to scan only the threads of the local
chip and not the whole machine.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/pnv_xive.c | 13 +++++++------
hw/ppc/pnv.c | 17 +++++++++++++++++
include/hw/ppc/pnv.h | 2 ++
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index ec8349ee4a..b2ab2ccc91 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1400,12 +1400,13 @@ static const MemoryRegionOps pnv_xive_ic_lsi_ops = {
*/
/*
- * When the TIMA is accessed from the indirect page, the thread id
- * (PIR) has to be configured in the IC registers before. This is used
- * for resets and for debug purpose also.
+ * When the TIMA is accessed from the indirect page, the thread id of
+ * the target CPU is configured in the PC_TCTXT_INDIR0 register before
+ * use. This is used for resets and for debug purpose also.
*/
static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive)
{
+ PnvChip *chip = xive->chip;
uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3];
PowerPCCPU *cpu = NULL;
int pir;
@@ -1415,15 +1416,15 @@ static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive
*xive)
return NULL;
}
- pir = GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir) & 0xff;
- cpu = ppc_get_vcpu_by_pir(pir);
+ pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir);
+ cpu = pnv_chip_find_cpu(chip, pir);
if (!cpu) {
xive_error(xive, "IC: invalid PIR %x for indirect access", pir);
return NULL;
}
/* Check that HW thread is XIVE enabled */
- if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
xive_error(xive, "IC: CPU %x is not enabled", pir);
}
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d899c83e52..8f688f4efc 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1371,6 +1371,23 @@ static void pnv_chip_class_init(ObjectClass *klass, void
*data)
dc->desc = "PowerNV Chip";
}
+PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
+{
+ int i, j;
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pc = chip->cores[i];
+ CPUCore *cc = CPU_CORE(pc);
+
+ for (j = 0; j < cc->nr_threads; j++) {
+ if (ppc_cpu_pir(pc->threads[j]) == pir) {
+ return pc->threads[j];
+ }
+ }
+ }
+ return NULL;
+}
+
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 12b0169a40..a58cfea3f2 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -162,6 +162,8 @@ typedef struct PnvChipClass {
#define PNV_CHIP_INDEX(chip) \
(((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
+PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
+
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
#define PNV_MACHINE(obj) \
OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
--
2.23.0
- [PULL 21/88] ppc/pnv: Quiesce some XIVE errors, (continued)
- [PULL 21/88] ppc/pnv: Quiesce some XIVE errors, David Gibson, 2019/12/16
- [PULL 24/88] ipmi: Add support to customize OEM functions, David Gibson, 2019/12/16
- [PULL 36/88] ppc/spapr: Implement the XiveFabric interface, David Gibson, 2019/12/16
- [PULL 22/88] ppc/xive: Introduce OS CAM line helpers, David Gibson, 2019/12/16
- [PULL 25/88] ppc/pnv: Add HIOMAP commands, David Gibson, 2019/12/16
- [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper, David Gibson, 2019/12/16
- [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT, David Gibson, 2019/12/16
- [PULL 34/88] ppc/xive: Introduce a XiveFabric interface, David Gibson, 2019/12/16
- [PULL 35/88] ppc/pnv: Implement the XiveFabric interface, David Gibson, 2019/12/16
- [PULL 41/88] spapr/xics: Configure number of servers in KVM, David Gibson, 2019/12/16
- [PULL 33/88] ppc/pnv: Fix TIMA indirect access,
David Gibson <=
- [PULL 29/88] ppc/pnv: Instantiate cores separately, David Gibson, 2019/12/16
- [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper, David Gibson, 2019/12/16
- [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces, David Gibson, 2019/12/16
- [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model, David Gibson, 2019/12/16
- [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter, David Gibson, 2019/12/16
- [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller, David Gibson, 2019/12/16
- [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT, David Gibson, 2019/12/16
- [PULL 39/88] linux-headers: Update, David Gibson, 2019/12/16
- [PULL 42/88] spapr/xive: Configure number of servers in KVM, David Gibson, 2019/12/16
- [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler, David Gibson, 2019/12/16