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[PATCH v1 36/36] target/riscv: Allow enabling the Hypervisor extension
From: |
Alistair Francis |
Subject: |
[PATCH v1 36/36] target/riscv: Allow enabling the Hypervisor extension |
Date: |
Mon, 9 Dec 2019 10:12:14 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.c | 5 +++++
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ac8f53a49d..f087bc2c8b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -453,6 +453,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (cpu->cfg.ext_u) {
target_misa |= RVU;
}
+ if (cpu->cfg.ext_h) {
+ target_misa |= RVH;
+ }
set_misa(env, RVXLEN | target_misa);
}
@@ -498,6 +501,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+ /* This is experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 84a07971dc..53bc6af5f7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -261,6 +261,7 @@ typedef struct RISCVCPU {
bool ext_c;
bool ext_s;
bool ext_u;
+ bool ext_h;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
--
2.24.0
- [PATCH v1 26/36] target/riscv: Remove the hret instruction, (continued)
- [PATCH v1 26/36] target/riscv: Remove the hret instruction, Alistair Francis, 2019/12/09
- [PATCH v1 27/36] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/12/09
- [PATCH v1 28/36] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/12/09
- [PATCH v1 29/36] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/12/09
- [PATCH v1 30/36] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/12/09
- [PATCH v1 31/36] target/riscv: Implement second stage MMU, Alistair Francis, 2019/12/09
- [PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails, Alistair Francis, 2019/12/09
- [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions, Alistair Francis, 2019/12/09
- [PATCH v1 34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/12/09
- [PATCH v1 35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2019/12/09
- [PATCH v1 36/36] target/riscv: Allow enabling the Hypervisor extension,
Alistair Francis <=
- Re: [PATCH v1 00/36] Add RISC-V Hypervisor Extension v0.5, Aleksandar Markovic, 2019/12/09