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Re: [PATCH 06/10] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_s

From: Niek Linnenbank
Subject: Re: [PATCH 06/10] arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()
Date: Fri, 6 Dec 2019 21:01:49 +0100

Hey Peter,

On Fri, Dec 6, 2019 at 3:25 PM Peter Maydell <address@hidden> wrote:
On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank <address@hidden> wrote:
> This change ensures that the FPU can be accessed in Non-Secure mode
> when the CPU core is reset using the arm_set_cpu_on() function call.
> The NSACR.{CP11,CP10} bits define the exception level required to
> access the FPU in Non-Secure mode. Without these bits set, the CPU
> will give an undefined exception trap on the first FPU access for the
> secondary cores under Linux.
> Fixes: fc1120a7f5
> Signed-off-by: Niek Linnenbank <address@hidden>
> ---

Oops, another place where we failed to realise the ramifications
of making NSACR actually do something.

Since this is a bugfix I'm going to fish it out of this patchset
and apply it to target-arm.next with a cc: stable.

Thanks for the catch!
Sure, I'm happy to help. Note that I only tested this fix with
the Allwinner H3 SoC patches that I'm working on.

OK, I'll keep an eye out for it. Once it is solved in master, I'll remove this patch from the patch series.

-- PMM

Niek Linnenbank

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