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Re: [PATCH 02/11] target/arm: Add arm_mmu_idx_is_stage1
From: |
Peter Maydell |
Subject: |
Re: [PATCH 02/11] target/arm: Add arm_mmu_idx_is_stage1 |
Date: |
Fri, 6 Dec 2019 19:00:12 +0000 |
On Tue, 3 Dec 2019 at 22:53, Richard Henderson
<address@hidden> wrote:
>
> Use a common predicate for querying stage1-ness.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/internals.h | 11 +++++++++++
> target/arm/helper.c | 8 +++-----
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 49dac2a677..850f204f14 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1034,6 +1034,17 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState
> *env)
> ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
> #endif
>
> +static inline bool arm_mmu_idx_is_stage1(ARMMMUIdx mmu_idx)
> +{
> + switch (mmu_idx) {
> + case ARMMMUIdx_Stage1_E0:
> + case ARMMMUIdx_Stage1_E1:
> + return true;
> + default:
> + return false;
> + }
> +}
This definition of 'stage 1' doesn't match the architecture's,
which has a lot more than 2 things that are stage1; eg whatever
your renaming is calling S1E2, S1E3, etc are all stage 1.
(That's why those names have 'S1' in them: they're stage 1
translation stages.)
thanks
-- PMM
- [PATCH 00/11] target/arm: Implement ARMv8.1-PAN + ARMv8.2-ATS1E1, Richard Henderson, 2019/12/03
- [PATCH 02/11] target/arm: Add arm_mmu_idx_is_stage1, Richard Henderson, 2019/12/03
- [PATCH 01/11] cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN, Richard Henderson, 2019/12/03
- [PATCH 04/11] target/arm: Reduce CPSR_RESERVED, Richard Henderson, 2019/12/03
- [PATCH 06/11] target/arm: Update MSR access for PAN, Richard Henderson, 2019/12/03
- [PATCH 07/11] target/arm: Update arm_mmu_idx_el for PAN, Richard Henderson, 2019/12/03
- [PATCH 05/11] target/arm: Add isar_feature tests for PAN + ATS1E1, Richard Henderson, 2019/12/03