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Re: [PATCH v5 18/22] target/arm: Enable MTE


From: Peter Maydell
Subject: Re: [PATCH v5 18/22] target/arm: Enable MTE
Date: Thu, 5 Dec 2019 18:23:01 +0000

On Fri, 11 Oct 2019 at 14:50, Richard Henderson
<address@hidden> wrote:
>
> We now implement all of the components of MTE, without actually
> supporting any tagged memory.  All MTE instructions will work,
> trivially, so we can enable support.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/cpu.c   | 10 ++++++++++
>  target/arm/cpu64.c |  1 +
>  2 files changed, 11 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 2399c14471..12fffa3ee4 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -209,6 +209,16 @@ static void arm_cpu_reset(CPUState *s)
>           * make no difference to the user-level emulation.
>           */
>          env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
> +        /* Enable MTE allocation tags.  */
> +        env->cp15.hcr_el2 |= HCR_ATA;
> +        env->cp15.scr_el3 |= SCR_ATA;
> +        env->cp15.sctlr_el[1] |= SCTLR_ATA0;
> +        /* Enable synchronous tag check failures.  */
> +        env->cp15.sctlr_el[1] |= 1ull << 38;

Isn't this making assumptions about the Linux ABI for
memtag (ie that it actually will expose it to userspace
and that it will make tag check failures synchronous)?

> +#ifdef TARGET_AARCH64
> +        /* Set MTE seed to non-zero value, otherwise RandomTag fails.  */
> +        env->cp15.rgsr_el1 = 0x123400;
> +#endif

Does anything go wrong if we don't bother with the #ifdef?

>  #else
>          /* Reset into the highest available EL */
>          if (arm_feature(env, ARM_FEATURE_EL3)) {
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index d7f5bf610a..ac1e2dc2c4 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -350,6 +350,7 @@ static void aarch64_max_initfn(Object *obj)
>
>          t = cpu->isar.id_aa64pfr1;
>          t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
> +        t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
>          cpu->isar.id_aa64pfr1 = t;
>
>          t = cpu->isar.id_aa64mmfr1;
> --

thanks
-- PMM



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