Re: [RFC 0/1] ATI R300 emulated grpahics card V2

[BALATON Zoltan]

On Thu, 28 Nov 2019, Gerd Hoffmann wrote:
> The infrastructure to branch into model-specific code is pretty rough
> right now, we might refine that, for example with some helper functions
> (ati_get_model() returning an enum, or ati_is_$model() functions
> returning bool, or both).

Maybe we could define ATI_IS_$MODEL macros to save some typing but I 
thought it's not much better than the current if() and also model specific 
functions could be grouped into separate ati_$model files so we don't need 
too many branches in the main file.

> Trouble-shooting linux guests shouldn't be too hard, you have the source
> code so you can check what the driver tries to do and you can add debug
> printk's to trace where exactly things are failing ;)

I think the main difficulties are to find out how the card works then once 
one gets that the next question is how to implement that in QEMU: e.g. how 
can we make the micro engine emulation run in a separate thread. I think 
it probably can be done with existing qemu thread and locking functions. 
The synchronisation between CPU and GPU should be solved by the protocol 
between them (after all in real hardware they also run parallel so this 
should have been solved). If so, the micro engine thread may only have to 
read memory packets then generate register accesses. For this to work the 
register access FIFO may also need to be added which is now missing as in 
current version register writes are executed immediately but once we have 
both the CPU and micro engine that can access registers we either need to 
implement the FIFO or have some synchronisation between the two. This 
needs some thought. (If we have the register write FIFO then the actual 
drawing can also be done in a separate thread which is more like what the 
real GPU does but to make it simple I did not try that in first version.)

If the microcode of the microengine/CCE could be reversed or is documented 
somewhere it may be easier to implement emulation of that instead of doing 
the packet parsing for all possible command packets of which there are 
quite a lot, but in the real GPU all those are handled by the small 
microcode. The ME/CCE is probably some VLIW processor with 40 bit 
instructions which likely have ops to read and write memory and access 
registers and maybe some branching and synchronisation but I have no idea 
how to find out which opcode means what. This microengine is probably very 
similar throughout the early Radeons, only the microcode changes so if we 
could implement that it might work for several cards (also even for 
Rage128Pro).

Regards,
BALATON Zoltan