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Re: [PATCH] target/arm: Honor HCR_EL2.TID3 trapping requirements
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH] target/arm: Honor HCR_EL2.TID3 trapping requirements |
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Date: |
Tue, 26 Nov 2019 12:46:32 +0000 |
On Mon, 25 Nov 2019 at 17:49, Marc Zyngier <address@hidden> wrote:
> I also had a look at TID0, but couldn't find any of the Jazelle
> stuff in QEMU...
We implement only "minimal Jazelle", ie the minimal set of
registers needed to be architecturally compliant for an
implementation without Jazelle.
thanks
-- PMM
Re: [PATCH] target/arm: Honor HCR_EL2.TID3 trapping requirements, Richard Henderson, 2019/11/26
Re: [PATCH] target/arm: Honor HCR_EL2.TID3 trapping requirements, Richard Henderson, 2019/11/26