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Re: [PATCH 4/4] watchdog/aspeed: Fix AST2600 frequency behaviour
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From: |
Joel Stanley |
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Subject: |
Re: [PATCH 4/4] watchdog/aspeed: Fix AST2600 frequency behaviour |
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Date: |
Wed, 13 Nov 2019 00:48:41 +0000 |
On Tue, 12 Nov 2019 at 07:56, Cédric Le Goater <address@hidden> wrote:
>
> On 12/11/2019 07:40, Joel Stanley wrote:
> > The AST2600 control register sneakily changed the meaning of bit 4
> > without anyone noticing. It no longer controls the 1MHz vs APB clock
> > select, and instead always runs at 1MHz.
> >
> > The AST2500 was always 1MHz too, but it retained bit 4, making it read
> > only. We can model both using the same fixed 1MHz calculation.
> >
> > Fixes: ea29711f467f ("watchdog/aspeed: Fix AST2600 control reg behaviour")
>
> which commit is that ^ ? Did you mean :
>
> Fixes: 6b2b2a703cad ("hw: wdt_aspeed: Add AST2600 support")
Yes. Thanks for catching that.
- [PATCH 0/4] arm/aspeed: Watchdog and SDRAM fixes, Joel Stanley, 2019/11/12
- [PATCH 1/4] aspeed/sdmc: Make ast2600 default 1G, Joel Stanley, 2019/11/12
- [PATCH 2/4] aspeed/scu: Fix W1C behavior, Joel Stanley, 2019/11/12
- [PATCH 3/4] watchdog/aspeed: Improve watchdog timeout message, Joel Stanley, 2019/11/12
- [PATCH 4/4] watchdog/aspeed: Fix AST2600 frequency behaviour, Joel Stanley, 2019/11/12
- Re: [PATCH 0/4] arm/aspeed: Watchdog and SDRAM fixes, no-reply, 2019/11/12