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[PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting
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From: |
Alistair Francis |
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Subject: |
[PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting |
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Date: |
Fri, 25 Oct 2019 16:23:54 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 12a10e8679..bb4557df16 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -39,12 +39,27 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
target_ulong mstatus_mie = get_field(*env->mstatus, MSTATUS_MIE);
target_ulong mstatus_sie = get_field(*env->mstatus, MSTATUS_SIE);
+ target_ulong vsstatus_sie = get_field(env->mstatus_novirt, MSTATUS_SIE);
+
target_ulong pending = env->mip & *env->mie;
- target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M &&
mstatus_mie);
- target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S &&
mstatus_sie);
+ target_ulong hspending = env->mip_novirt & env->mie_novirt;
+
+ target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M &&
mstatus_mie);
+ target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S &&
mstatus_sie);
+ target_ulong vsie = env->priv < PRV_S || (env->priv == PRV_S &&
vsstatus_sie);
+
target_ulong irqs = (pending & ~env->mideleg & -mie) |
(pending & env->mideleg & -sie);
+ if (riscv_cpu_virt_enabled(env)) {
+ target_ulong pending_hs_irq = hspending & -vsie;
+
+ if (pending_hs_irq) {
+ riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
+ return ctz64(pending_hs_irq);
+ }
+ }
+
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
--
2.23.0
- [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled, (continued)
- [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/10/25
- [PATCH v2 07/27] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/10/25
- [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/10/25
- [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/10/25
- [PATCH v2 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/10/25
- [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/10/25
- [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/10/25
- [PATCH v2 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/10/25
- [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/10/25
- [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/10/25
- [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting,
Alistair Francis <=
- [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/10/25
- [PATCH v2 12/27] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/10/25
- [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/10/25
- [PATCH v2 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/10/25
- [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/10/25
- [PATCH v2 24/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/10/25
- [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/10/25
- [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2019/10/25
- [PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/10/25
- [PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/10/25