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Re: [PATCH 1/2] spapr: Introduce a interrupt presenter reset handler
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From: |
Greg Kurz |
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Subject: |
Re: [PATCH 1/2] spapr: Introduce a interrupt presenter reset handler |
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Date: |
Fri, 18 Oct 2019 09:46:04 +0200 |
On Thu, 17 Oct 2019 16:42:40 +0200
Cédric Le Goater <address@hidden> wrote:
> The interrupt presenters are not reseted today. Extend the sPAPR IRQ
> backend with a new cpu_intc_reset() handler which will be called by
> the CPU reset handler.
>
> spapr_realize_vcpu() is modified to call the CPU reset only after the
> the intc presenter has been created.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
> ---
> include/hw/ppc/spapr_irq.h | 4 ++++
> include/hw/ppc/xics.h | 1 +
> include/hw/ppc/xive.h | 1 +
> hw/intc/spapr_xive.c | 8 ++++++++
> hw/intc/xics.c | 5 +++++
> hw/intc/xics_spapr.c | 8 ++++++++
> hw/intc/xive.c | 11 ++++++++---
> hw/ppc/spapr_cpu_core.c | 8 ++++++--
> hw/ppc/spapr_irq.c | 21 +++++++++++++++++++++
> 9 files changed, 62 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
> index 5e150a667902..78327496c102 100644
> --- a/include/hw/ppc/spapr_irq.h
> +++ b/include/hw/ppc/spapr_irq.h
> @@ -52,6 +52,8 @@ typedef struct SpaprInterruptControllerClass {
> */
> int (*cpu_intc_create)(SpaprInterruptController *intc,
> PowerPCCPU *cpu, Error **errp);
> + int (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu,
> + Error **errp);
Looking at the rest of the patch, it seems that we don't need error
reporting. I suggest you make this void and drop the errp parameter.
> int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi,
> Error **errp);
> void (*free_irq)(SpaprInterruptController *intc, int irq);
> @@ -68,6 +70,8 @@ void spapr_irq_update_active_intc(SpaprMachineState *spapr);
>
> int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
> PowerPCCPU *cpu, Error **errp);
> +int spapr_irq_cpu_intc_reset(SpaprMachineState *spapr,
> + PowerPCCPU *cpu, Error **errp);
> void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon);
> void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
> void *fdt, uint32_t phandle);
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 1e6a9300eb2b..602173c12250 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -161,6 +161,7 @@ void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
> uint32_t icp_accept(ICPState *ss);
> uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
> void icp_eoi(ICPState *icp, uint32_t xirr);
> +void icp_reset(ICPState *icp);
>
> void ics_write_xive(ICSState *ics, int nr, int server,
> uint8_t priority, uint8_t saved_priority);
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index fd3319bd3202..99381639f50c 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -415,6 +415,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset,
> unsigned size);
>
> void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
> Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
> +void xive_tctx_reset(XiveTCTX *tctx);
>
> static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
> {
> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> index ba32d2cc5b0f..0c3acf1a4192 100644
> --- a/hw/intc/spapr_xive.c
> +++ b/hw/intc/spapr_xive.c
> @@ -553,6 +553,13 @@ static int
> spapr_xive_cpu_intc_create(SpaprInterruptController *intc,
> return 0;
> }
>
> +static int spapr_xive_cpu_intc_reset(SpaprInterruptController *intc,
> + PowerPCCPU *cpu, Error **errp)
> +{
> + xive_tctx_reset(spapr_cpu_state(cpu)->tctx);
> + return 0;
> +}
> +
> static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int
> val)
> {
> SpaprXive *xive = SPAPR_XIVE(intc);
> @@ -697,6 +704,7 @@ static void spapr_xive_class_init(ObjectClass *klass,
> void *data)
> sicc->activate = spapr_xive_activate;
> sicc->deactivate = spapr_xive_deactivate;
> sicc->cpu_intc_create = spapr_xive_cpu_intc_create;
> + sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset;
> sicc->claim_irq = spapr_xive_claim_irq;
> sicc->free_irq = spapr_xive_free_irq;
> sicc->set_irq = spapr_xive_set_irq;
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index b5ac408f7b74..652771d6a5a5 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -295,6 +295,11 @@ static void icp_reset_handler(void *dev)
> }
> }
>
> +void icp_reset(ICPState *icp)
> +{
> + icp_reset_handler(icp);
> +}
> +
> static void icp_realize(DeviceState *dev, Error **errp)
> {
> ICPState *icp = ICP(dev);
> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> index 4f64b9a9fc66..c0b2a576effe 100644
> --- a/hw/intc/xics_spapr.c
> +++ b/hw/intc/xics_spapr.c
> @@ -346,6 +346,13 @@ static int
> xics_spapr_cpu_intc_create(SpaprInterruptController *intc,
> return 0;
> }
>
> +static int xics_spapr_cpu_intc_reset(SpaprInterruptController *intc,
> + PowerPCCPU *cpu, Error **errp)
> +{
> + icp_reset(spapr_cpu_state(cpu)->icp);
> + return 0;
> +}
> +
> static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq,
> bool lsi, Error **errp)
> {
> @@ -433,6 +440,7 @@ static void ics_spapr_class_init(ObjectClass *klass, void
> *data)
> sicc->activate = xics_spapr_activate;
> sicc->deactivate = xics_spapr_deactivate;
> sicc->cpu_intc_create = xics_spapr_cpu_intc_create;
> + sicc->cpu_intc_reset = xics_spapr_cpu_intc_reset;
> sicc->claim_irq = xics_spapr_claim_irq;
> sicc->free_irq = xics_spapr_free_irq;
> sicc->set_irq = xics_spapr_set_irq;
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index d420c6571e14..0ae3f9b1efe4 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -547,7 +547,7 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor
> *mon)
> }
> }
>
> -static void xive_tctx_reset(void *dev)
> +static void xive_tctx_reset_handler(void *dev)
> {
> XiveTCTX *tctx = XIVE_TCTX(dev);
>
> @@ -568,6 +568,11 @@ static void xive_tctx_reset(void *dev)
> ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);
> }
>
> +void xive_tctx_reset(XiveTCTX *tctx)
> +{
> + xive_tctx_reset_handler(tctx);
> +}
> +
> static void xive_tctx_realize(DeviceState *dev, Error **errp)
> {
> XiveTCTX *tctx = XIVE_TCTX(dev);
> @@ -608,12 +613,12 @@ static void xive_tctx_realize(DeviceState *dev, Error
> **errp)
> }
> }
>
> - qemu_register_reset(xive_tctx_reset, dev);
> + qemu_register_reset(xive_tctx_reset_handler, dev);
> }
>
> static void xive_tctx_unrealize(DeviceState *dev, Error **errp)
> {
> - qemu_unregister_reset(xive_tctx_reset, dev);
> + qemu_unregister_reset(xive_tctx_reset_handler, dev);
> }
>
> static int vmstate_xive_tctx_pre_save(void *opaque)
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index 3e4302c7d596..416aa75e5fba 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -33,6 +33,7 @@ static void spapr_cpu_reset(void *opaque)
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
> target_ulong lpcr;
> + SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
>
> cpu_reset(cs);
>
> @@ -77,9 +78,11 @@ static void spapr_cpu_reset(void *opaque)
> spapr_cpu->dtl_addr = 0;
> spapr_cpu->dtl_size = 0;
>
> - spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);
> + spapr_caps_cpu_apply(spapr, cpu);
>
> kvm_check_mmu(cpu, &error_fatal);
> +
> + spapr_irq_cpu_intc_reset(spapr, cpu, &error_fatal);
So now, interrupt presenters are reset twice: from here and
from qemu_devices_reset(). Not a big deal, but if you add
something equivalent in the pnv machine, then the presenters
no longer need to call qemu_register_reset() at all.
> }
>
> void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
> target_ulong r3)
> @@ -235,12 +238,13 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu,
> SpaprMachineState *spapr,
> kvmppc_set_papr(cpu);
>
> qemu_register_reset(spapr_cpu_reset, cpu);
> - spapr_cpu_reset(cpu);
>
> if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) {
> goto error_unregister;
> }
>
> + spapr_cpu_reset(cpu);
> +
> if (!sc->pre_3_0_migration) {
> vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
> cpu->machine_data);
> diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
> index bb91c61fa000..5d2b64029cd5 100644
> --- a/hw/ppc/spapr_irq.c
> +++ b/hw/ppc/spapr_irq.c
> @@ -220,6 +220,27 @@ int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
> return 0;
> }
>
> +int spapr_irq_cpu_intc_reset(SpaprMachineState *spapr,
> + PowerPCCPU *cpu, Error **errp)
> +{
> + SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
> + int i;
> + int rc;
> +
> + for (i = 0; i < ARRAY_SIZE(intcs); i++) {
> + SpaprInterruptController *intc = intcs[i];
> + if (intc) {
> + SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc);
> + rc = sicc->cpu_intc_reset(intc, cpu, errp);
> + if (rc < 0) {
> + return rc;
> + }
> + }
> + }
> +
> + return 0;
> +}
> +
> static void spapr_set_irq(void *opaque, int irq, int level)
> {
> SpaprMachineState *spapr = SPAPR_MACHINE(opaque);