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[PULL 60/68] aspeed: Parameterise number of MACs
From: |
Peter Maydell |
Subject: |
[PULL 60/68] aspeed: Parameterise number of MACs |
Date: |
Mon, 14 Oct 2019 17:03:56 +0100 |
From: Joel Stanley <address@hidden>
To support the ast2600's four MACs allow SoCs to specify the number
they have, and create that many.
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: - included a check on sc->macs_num when realizing the macs
- included interrupt definitions for the AST2600 ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/arm/aspeed_soc.h | 5 ++++-
hw/arm/aspeed_ast2600.c | 10 ++++++++--
hw/arm/aspeed_soc.c | 6 ++++--
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 67c59956f83..088a5d10818 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -30,7 +30,7 @@
#define ASPEED_SPIS_NUM 2
#define ASPEED_WDTS_NUM 4
#define ASPEED_CPUS_NUM 2
-#define ASPEED_MACS_NUM 2
+#define ASPEED_MACS_NUM 4
typedef struct AspeedSoCState {
/*< private >*/
@@ -69,6 +69,7 @@ typedef struct AspeedSoCClass {
uint64_t sram_size;
int spis_num;
int wdts_num;
+ int macs_num;
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
@@ -114,6 +115,8 @@ enum {
ASPEED_I2C,
ASPEED_ETH1,
ASPEED_ETH2,
+ ASPEED_ETH3,
+ ASPEED_ETH4,
ASPEED_SDRAM,
ASPEED_XDMA,
};
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index a4f0fafab7c..25d2c2d05d6 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -32,7 +32,9 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_SPI1] = 0x1E630000,
[ASPEED_SPI2] = 0x1E641000,
[ASPEED_ETH1] = 0x1E660000,
+ [ASPEED_ETH3] = 0x1E670000,
[ASPEED_ETH2] = 0x1E680000,
+ [ASPEED_ETH4] = 0x1E690000,
[ASPEED_VIC] = 0x1E6C0000,
[ASPEED_SDMC] = 0x1E6E0000,
[ASPEED_SCU] = 0x1E6E2000,
@@ -88,6 +90,9 @@ static const int aspeed_soc_ast2600_irqmap[] = {
[ASPEED_I2C] = 110, /* 110 -> 125 */
[ASPEED_ETH1] = 2,
[ASPEED_ETH2] = 3,
+ [ASPEED_ETH3] = 32,
+ [ASPEED_ETH4] = 33,
+
};
static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
@@ -173,7 +178,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
OBJECT(&s->scu), &error_abort);
}
- for (i = 0; i < ASPEED_MACS_NUM; i++) {
+ for (i = 0; i < sc->macs_num; i++) {
sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
}
@@ -397,7 +402,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev,
Error **errp)
}
/* Net */
- for (i = 0; i < nb_nics; i++) {
+ for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
&err);
@@ -470,6 +475,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc,
void *data)
sc->sram_size = 0x10000;
sc->spis_num = 2;
sc->wdts_num = 4;
+ sc->macs_num = 4;
sc->irqmap = aspeed_soc_ast2600_irqmap;
sc->memmap = aspeed_soc_ast2600_memmap;
sc->num_cpus = 2;
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index a063be9fd79..6defb143acd 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -198,7 +198,7 @@ static void aspeed_soc_init(Object *obj)
OBJECT(&s->scu), &error_abort);
}
- for (i = 0; i < ASPEED_MACS_NUM; i++) {
+ for (i = 0; i < sc->macs_num; i++) {
sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
}
@@ -372,7 +372,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
}
/* Net */
- for (i = 0; i < nb_nics; i++) {
+ for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
&err);
@@ -455,6 +455,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc,
void *data)
sc->sram_size = 0x8000;
sc->spis_num = 1;
sc->wdts_num = 2;
+ sc->macs_num = 2;
sc->irqmap = aspeed_soc_ast2400_irqmap;
sc->memmap = aspeed_soc_ast2400_memmap;
sc->num_cpus = 1;
@@ -478,6 +479,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc,
void *data)
sc->sram_size = 0x9000;
sc->spis_num = 2;
sc->wdts_num = 3;
+ sc->macs_num = 2;
sc->irqmap = aspeed_soc_ast2500_irqmap;
sc->memmap = aspeed_soc_ast2500_memmap;
sc->num_cpus = 1;
--
2.20.1
- [PULL 49/68] watchdog/aspeed: Introduce an object class per SoC, (continued)
- [PULL 49/68] watchdog/aspeed: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 52/68] aspeed/smc: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 51/68] aspeed/smc: Introduce segment operations, Peter Maydell, 2019/10/14
- [PULL 53/68] hw/gpio: Add in AST2600 specific implementation, Peter Maydell, 2019/10/14
- [PULL 55/68] aspeed/i2c: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 54/68] aspeed/i2c: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 58/68] m25p80: Add support for w25q512jv, Peter Maydell, 2019/10/14
- [PULL 59/68] aspeed: Add an AST2600 eval board, Peter Maydell, 2019/10/14
- [PULL 56/68] aspeed: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 57/68] aspeed/soc: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 60/68] aspeed: Parameterise number of MACs,
Peter Maydell <=
- [PULL 61/68] aspeed: add support for the Aspeed MII controller of the AST2600, Peter Maydell, 2019/10/14
- [PULL 62/68] aspeed/soc: Add ASPEED Video stub, Peter Maydell, 2019/10/14
- [PULL 63/68] hw/arm/raspi: Use the IEC binary prefix definitions, Peter Maydell, 2019/10/14
- [PULL 64/68] hw/arm/bcm2835_peripherals: Improve logging, Peter Maydell, 2019/10/14
- [PULL 65/68] hw/arm/bcm2835_peripherals: Name various address spaces, Peter Maydell, 2019/10/14
- [PULL 66/68] hw/arm/bcm2835: Rename some definitions, Peter Maydell, 2019/10/14
- [PULL 68/68] hw/misc/bcm2835_mbox: Add trace events, Peter Maydell, 2019/10/14
- [PULL 67/68] hw/arm/bcm2835: Add various unimplemented peripherals, Peter Maydell, 2019/10/14